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Single Clock Domain. Otherwise madness!

Posted by Tony Lauck (A) on March 26, 2012 at 10:37:50

In Reply to: RE: Reminder... posted by rick_m on March 26, 2012 at 09:07:24:

Don't agree with your comments about clock domains. There is no hope for SPDIF or other schemes that don't force the transport to synchronize to the receiver's clock. If one is forced to work with unsynchronizable input one will have to go the reclocker approach and require suitably tight clock tolerances on the transport, suitably large FIFO buffers, suitably large stop/play user interface latencies and restricted play list lengths. But SPDIF is a bad system design. Why make a hard problem even more difficult. One has to throw away broken standards if one is ever going to make progress.

Therefore, I am assuming that the input has already been synchronized into a single local DAC clock domain. This can be accomplished by various means, e.g. a traditional reclocker with big buffer and high latency, slaving the transport so that it is frequency locked to a word clock or master clock emitted by the DAC or async USB interface with some kind of circular buffer to accommodate the variable filling by packets and the steady emptying by samples or bits. I assume that all the circuitry in the input clock domain is powered separately from all the other equipment in the DAC and provides a simple interface, e.g. for a monaural DSD DAC there would be two signals: a clock signal and a data signal, with suitable setup and hold times to ensure that the data signal never changed while the clock signal was asserted. The clock signal goes from the DAC proper to the input domain while the data signal goes from the input domain to the DAC proper. At this point all synchronization has been completed and all of the bits that are passed on are assumed to be correct, otherwise there has been a data error on the input receiver, something that need not happen with a half-decent implementation. The clock signal will have variations due to noise, but this noise will be locally generated. The data signal will have noise, in the form of timing variations and amplitude variations, to be dealt with as below.

Next there would be some number of stages of a shift register, individually clocked from the local master clock and some kind of multi-phase clock scheme such that there are defined periods between loading each stage where the input at the previous stage has had time to thoroughly be restored, i.e. amplitude variations removed from a previous transition, or leakage from gates. (Note that the output voltage of an Or gate may be slightly different depending on whether one or two input signals are asserted, even though logically the output should be equally true.) This also means that the transition time of a flip flop that is changing state as a result of a clock pulse will vary slightly according to how high the incoming signal level is that is being strobed. One has to look at the circuit design and layout carefully to make sure that each stage of the shift register reduces these timing variations as well as the obvious reduction of amplitude variations. If one clocks slowly enough one can use multiple stages of inverters between flip flops to clean up any leakage by the gates from previous stages. One has to get down to the transistor level and transmission line (layout level) and understand all the parasitics involved, etc. if one wants to do this right.

In your terminology, each stage of this synchronously running shift register copies a slightly dirty symbol and produces a new symbol that is slightly cleaner with respect to any disturbances in the original. (There will be a residual dirtiness at each stage caused by timing variations in the clock and clock distribution and power and ground noise.) After some number of stages of this buffering these local effects will completely dominate any source effects so that what one hears will be transport independent. Whether it's any good or not is a different issue of course and that will depend on the circuits that take these bits and turn them into an analog waveform. In the case of DSD this could be nothing but a two stage buffer followed by a passive low pass filter. Such a DSD DAC could be very light weight, perhaps having no more than a few dozen gates that run in the local clock domain.

I think the number of transistors required is small enough that one could do a suitable SPICE simulation to validate and quantify these concepts. If one built this device it would also be possible to create test signals to measure how much variations on the input are attenuated by the shift register. (The locally generated variations can be taken out by statistical averaging.) BTW, I believe that each stage of this register is going to have to be implemented in a separate chip. It may be possible to work with off the shelf logic chips. There aren't many gates required in this design so this would be practical. Putting a bunch of gates in an FPGA is unlikely to provide isolation measured in amounts such as -160 dB.

This design does not require any computation, so there is no need for any processors, software, etc. that can be tweaked. It consists of a bunch of transistors that are configured in a mixed signal configuration but which are analyzed as analog components. All of the complex software goes elsewhere, many feet away, possibly isolated by multiple boxes. Some of this software may be fairly complex, e.g. a PCM to DSD128 modulator, but at least at this point bits are just bits if the DAC works as intended.

In this design, one would want to put the DAC on the "Tranquility Base". :-)

Tony Lauck

"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar

Edits: 03/26/12

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