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In Reply to: RE: Single Clock Domain. Otherwise madness! posted by rick_m on March 28, 2012 at 08:36:48:
I suggest you look at some sample circuit diagrams for a typical gate. One such involves two pull down transistors with their output in parallel connected to a source via a pull up resistor. In this case, the output level when both transistors are "on" is going to be lower than when only one transistor is "on". What this means is that if one input is held "on" the voltage level on the output will still be a function of the fluctuating voltage input on the other input. However, the output will definitely be fluctuating less than the input, e.g. the input could be fluctuating across the full range of logic levels, while the output necessarily fluctuates about the region corresponding to a legal logic level (e.g. 25% of the full range). Now imagine that the flucutating signal is being gated into the input of a latch by a clock. The output of this gate will have a small amount of fluctuation and this output will be input to one input of one of the gates in the latch. So the output of the latch will also be fluctuating slightly with the input signal, even if there is no clock pulse to enable the gate sufficiently to "change" the state of the latch. This is just one reason why a single stage of a flip-flop does not produce an output that is uncorrelated with the input signal. In the absence of clock pulses, this is the simple analysis, it becomes much more complicated when analyzing situations where the input voltage is fluctuating (but not changing logic levels) at the same time that the register is being strobed. Example: stage N of a shift registor is being loaded. At this clock phase, stage N-1 is not being loaded, so produces constant output (viewed as bits) or a certain amount of fluctuation (viewed as analog signal). In a 4-phase clock scheme for the shift register, stage N-2 is being loaded, hence there will be a complete change of logic level at roughly the same time stage stage N is being loaded. This means that at roughly the same time stage N is being loaded the voltage on one of its gates may be fluctuating due to slight leakage through the unclocked stage N-1. It is reasonable to assume that this will affect the rate at which stage N latches into the new state, but here the circuit design issues will be less obvious. It would be my guess that a SPICE simulation would show these effects if the circuitry can be adequately modeled at the transistor level. I also suspect that it would be practical to set up a test bed and measure these effects as well, although it would be difficult to eliminate coupling caused by "gate leakage" from other forms of leakage, e.g. "ground bounce". This is something for a circuit designer with mixed signal expertise to carefully consider. It is not something that most people, myself included, have the skills or tools to investigate.
It is possible to conduct experiments to distinguish whether propagation comes through the signal path vs. through power and ground. Suppose one has two signal sources and two isolation/outputs. These can be connected together (via jumpers) in one of two ways, direct vs. crossed. One provides two identical input signals except that one is deliberately distorted by addition of noise, including noise that is carefully synchronized to the clocks). One then compares the various possible combinations of inputs, cross wiring and outputs and measures output noise. The layouts have to be symmetrical for this experiment to be valid. It is convenient to work with a single ended DSD DAC, i.e. treat the output of the final flip-flop directly as a DSD audio signal. Any jitter or AM modulation will appear at this point and using synchronous averaging it will be possible to correlate any coupled noise to a very low level by measuring over a long time period (very narrow frequency band).
Audiophile hobbyists can conduct similar experiments where the sources are separate boxes. So, for example, if an untweaked PC is coupling area digital cable it will affect the output only when it is actually connected to a DAC, but if the coupling were through power wiring it would still pollute the sound from being powered up and playing, even if the DAC were connected and playing music from a separate transport. The key to these experiments is some reliable means of detecting when sonic pollution is occurring. Believers in subjective listening can do these experiments by ear if they have sufficient time, patience and self-discipline.
Note that even if complete isolation of all forms of input noise is provided by a DAC, it is likely that some audiophiles would still complain that there was an effect. This likelihood provides strong demotivation for me to investigate this in detail or to get involved in the business designing and producing high end audio gear, for that matter. :-(
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
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Follow Ups
- RE: Single Clock Domain. Otherwise madness! - Tony Lauck 09:40:45 03/28/12 (2)
- RE: Single Clock Domain. Otherwise madness! - rick_m 07:48:38 03/29/12 (1)
- RE: Single Clock Domain. Otherwise madness! - Tony Lauck 08:14:15 03/29/12 (0)
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