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Upsamplers, DACs, jitter, shakes and analogue withdrawals, this is it.

Re: You might be interested in this ...

*** You force Audition to work with 16b internal precision. Craps out.
Read file, convert to 32b internal, the do all SRC, then back to
16b. Artefacts gone. Try it. ***

I'm sorry, but this is irrelevant, and also incorrect. I didn't "force" audition to work with 16bit internal precision (I can't anyway, because Audition always works internally at 32-bit fp precision. This has been true since Cool Edit days).

Remember: the original context was you claimed you have never seen SRC artefacts in Audition. I gave an example in which you can experience SRC artefacts in Audition. The example is also valid in the context of the topic of discussion.

Rather than exhorting me to "try it", why don't *you* try it, and show us the results. That way, *you* can make sure you are not "forcing" Audition to do anything.

*** I you read closer you'll know by now that *I* never discussed here anything in the context of jitter or jitter reduction (not one of my pet obsessions, have too many others ***

I'm sorry, but what you are obsessed about or not is irrelevant. You joined a topic about ASRC in DACs, and usually it's polite to try and stay within topic. If you want to talk about something else, start a new topic.

*** I referred to the existing FPGA ***

You still haven't provided any details. Which existing FPGA?

*** We talked a lot about SRC and concluded that many implementations, even those for non-real-time apps, are utterly faulty. ***

No, you concluded that they were faulty. I drew a different conclusion.

*** Well, since you pointed to src.infinitewave.ca and since that site indicates that SRC is almost never done right, methinks it became part of the discussion, not? ***

Can you show me exactly where on that site does it state that "SRC is almost never done right"?

That was an extrapolation and speculation made by you. All the site did was provide graphs. My view is that the graphs are consistent with the hypothesis that SRC implementations are a trade off between accuracy and speed. This trade off is important in the context of the topic of discussion (ASRC in DACs). If you want to discuss a different topic, such as "faulty" SRC implementations and the competency of the implementers, start a new thread :-) I may even join you there!


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  • Re: You might be interested in this ... - Christine Tham 14:10:30 03/06/07 (0)


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