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Re: Jitter at what point in the chain?

Howdy

What? I'd take your supposed counter example as an example of why my statement is right!

Jitter is insidious and (perhaps until recently) most designers haven't taken it seriously enough.

Just because the clock originates at the DAC (which is the best topology IMO) doesn't mean that all incoming jitter is eliminated. I have the EMM Labs CDSD and DAC6e which also uses a DAC sourced clock, and therefore can skip the evils of the clock recovery PLLs, etc. Unfortunately I can still hear the differences that better mechanical isolation make for the transport as well as the differences in changing power cords on the transport. None of this invalidates my statement, the timing errors of the returning clock and data still have effects that we wished they didn't.

-Ted

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