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Secret Jitter Path

Posted by John Swenson (A) on March 5, 2007 at 17:25:20

In Reply to: Re: We are not connecting here posted by Charles Hansen on March 4, 2007 at 16:50:26:

If you will allow me to interject here, there IS a secret jitter path, its the reclocker itself. So far nobody has yet come up with a reclocker that is completely imune to the jitter on the DATA input.

For reclocking everybody is using a CMOS flip-flop, in any logic chip all the inputs will cause current spikes on the VDD and VSS (power and ground) internal traces in the chip, package etc. These current spikes cause voltage drops across the resistances and inductances of the traces. The "threshold" where the chip senses the change in the clock signal (its actually much more complicated than that, but for simplicities sake I'll call it a simple threshold) varies with these voltages, so the point at which the flop sends the value through will change in time based on these signal induced variations in on chip power. This is jitter.

Now you may think "well if the input signal doesn't switch anywhere near the clock edge it doesn't matter", this is quite true, BUT the internal spikes frequently excite resonances in the chip which cause ringing on the rails which last quite a bit longer than the transition of the signal. The upshot is that reclocking fast changing signals (such as highly oversampled or upsampled signals) is not good. The slower the signals being reclocked the better. Going to faster logic just makes it worse, they cause even more internal ringing.

Then there is how you do the reclocking. If you use a chip with multiple flops per chips, and use it to reclock multiple signals, the jitter from all those inputs combine. The best is to use single flop per package in very tiny packages to cut down on the package inductance.

OK so what about feeding the ultra low jitter clock directly to the DAC and not reclocking the other signals, well you wind up with the same issues inside the DAC chip itself.

The best way is to do both, run the slowest signals you can get through a reclocker AND feed the direct clock signal into the DAC. Of course this is assuming synchronous reclocking, no PLLs etc, the low jitter clock is right next to the DAC chip and controls the rest of the system.

Note that the above says absolutely nothing about galvanic isolation from the source, this is talking about jitter on the data lines, which will pass through any type of isolation scheme, as a matter of fact most isolation schemes actually increase the jitter on the signals which is why I don't use them in my system.

So all these DACs that are running super upsampled, multi whatever high speed signals (which sound impressive in marketing blurbs) actually make the system MORE sensitive to jitter than the old slow systems.

And don't get me started on jitter and FIFOs, this has gone on long enough, but I hope you get the idea, there are REAL measurable ways jitter can still get through a synchronous resampled system.

If the designer takes all this into account and does everything just right, the amount of jitter that can get through is pretty small, but its still definately there.

John S.

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