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Jitter Research, Analysis & Measurement

Posted by cics (A) on March 24, 2008 at 12:55:55

Jitter Research, Analysis & Measurement

Abstract


Sound is better with the cMP (configured as Transport) and acting as Master. Conventional wisdom suggests a Transport slaved to a DAC is best. I held this view until now. Using the dCS Scarlatti Clock and trying many things (power cords, conditioners, high-end BNC cables) it failed to impress. A measurable way of understanding this apart from subjective listening is covered.

Background
Why cMP sending SRC (Secret Rabbit Code) upsampled 24/96 SPDIF via toslink is superior led to this work. Transports providing an (embedded) master or sample clock are meant to be inferior (as clock recovery is performed by a receiver chip). My subjective listening tests shows otherwise.

The asset test for great sound is whether I can listen to an entire CD (that I enjoy and am very familiar with) without feeling tired and uninvolved. Things like blind testing and focus groups don’t help much here. Alternatively, pretending things sound better (placebo stuff) is short-lived because as you make your way through an entire CD, reality sets in… Here are the results for the different setups:

1. cMP with RME HDSP 9652 slaved, Scarlatti Clock set for ‘No Dither’, DAC is AA Prestige SE. Sound is unpleasant with harsh / bright elements. There’s no way I could listen to an entire CD. Stop.
   
2. As 1 above but Scarlatti Clock set to ‘Dither’. Dithering helps exercise PLLs. A significant improvement over previous but still some subtle digital artifacts – spotlighting of high frequency content. Initial few seconds sounds nice but as you work your way through a track it starts wearing you down. HF spotlighting is fatiguing and a full CD listen is a stretch. Pause.
   
3. No Scarlatti Clock (RME set as Master), cMP > AA Prestige SE. cMP acts as master. No more spotlighting with a natural overall sound (treble is sweet and elegant). Play.
   
4. Repeat first 3 with dCS Scarlatti DAC. Same results. Scarlatti DAC makes for an improved sound over AA. Both exceptionally good.
   
5. cMP Transport & Scarlatti DAC slaved to Scarlatti Clock. This is how dCS expects the Scarlatti Clock to be used. Sound is very similar to 2, HF spotlighting! Listening to a CD is difficult with 3 still rendering a more natural sound.
   
6. cMP > Scarlatti DAC with Scarlatti Clock completely disconnected. This betters 3 - pure galvanic isolation is achieved (using toslink). RME and dCS suggest clock input implementations are galvanically isolated. (I’d like to see the physics of how this is achieved as my understanding of quantum physics suggests this to be impossible).

These tests were done using the E2140 processor. By upgrading to the E1200 processor, scenario 6 has lifted to a better level. Aside: switching to the Juli@ soundcard is equally impressive and it’s been tough making a call against the RME. Only after the E1200 upgrade, the RME soundcard performed better.

Of all things important in a system, natural bloom is by far the most important. Jitter (and incorrect upsampling) bedevils this – this is not artificial bloom which becomes apparent in a while and is fatiguing. Instead, the bloom being referred to is un-hyped and slightly understated but never fatiguing. This leads to sound that’s very lifelike and exhibits a real presence.

Computers superiority in jitter performance is not well understood. Consider this: SATA specifications demand strict jitter tolerances for which standards are defined (something like not exceeding 160ps peak). Computer manufacturers utilize jitter testing equipment measuring in femto seconds (a femto is a thousand fold less than a ps)! This is all very necessary to achieve very high bandwidths and extremely low bit error ratios.

Jitter Research
The late Julian Dunn laid the foundations for understanding jitter. His work is most impressive and can be found on the web. Jitter refers to timing errors of the master clock used in DACs and ADCs. The slightest errors in timing causes signal amplitude errors. Its effects can be modeled, simulated and measured.

Jitter is Random or Deterministic. Whilst random is easy to understand, deterministic jitter is not. There are 2 forms: data correlated and periodic. Data correlated refers to jitter arising when certain patterns of data is present. Periodic is cyclical and has a defined frequency. Over a single period (1/frequency), clock signals stretch then shrink but total time over the period remains accurate!

Random Jitter
Random Jitter impacts the DACs SNR. This is also modeled and as one would expect, for excellent SNR performance, random jitter must be low. Improvement in SNR is slow as large reductions in jitter are needed.

Another important ingredient is the sampling frequency. Higher the Fs, better the SNR. Each doubling of Fs results in ~3db improvement in SNR. This is inferred from Burr Brown’s very conservative formula for calculating DAC SNR.

Periodic Jitter
Periodic Jitter has a defined frequency and its distortion can be modeled. DACs (and ADCs) cause distortion (sideband noise) when subject to periodic jitter. For a given fundamental input frequency, the fundamental together with side bands (distortion) occur on either side (distanced by the jitter frequency). An example can be seen in figure 1.

Figure 1. Periodic jitter of 7ns (Jpp) at 3kHz for an actual 10kHz pure input tone. Sidebands of 7 & 13kHz occur and its distance from the fundamental is given by the jitter frequency (3kHz). Source: Audio Precision, “Measurement Techniques for Digital Audio” by Julian Dunn. Quote: “In this figure there are also “skirts” to the spectrum closer to the 10 kHz component. These are due to some low-frequency noise-like jitter in the system”.

Figure 1 shows sine wave periodic jitter affecting a 10kHz audio tone. Square wave jitter is more harmful giving rise to continuous sidebands throughout the audio band. The strength of these sidebands is determined using Dunn’s formula:

Figure 2. Sideband energy levels increase with higher audio frequencies and higher jitter levels (J as in Jpp). Note wi refers to: F (input audio frequency) 2 Pi. (This is called the angular frequency). For example, Jpp at 7ns acting on an input tone of 10 kHz gives sidebands at -79.2db (as in figure 1).

In simple English, this says the higher the input frequency and with increasing jitter (Jpp), the greater the strength (or energy) of the sideband distortions. Periodic jitter is more offensive than random jitter as its sidebands are aharmonic. Music is harmonic (extending into high frequencies) and when such jitter is present, much of the natural tone decay is polluted. Natural bloom is lost. Jitter does most damage in the higher frequencies, ie. when large voltage swings occur (called slewing) as this results in much greater signal amplitude errors.

Jitter Accumulates
There’s more to jitter than just Random and Periodic, for example:

• Interface jitter (transmission related timing errors – explaining why digital cables sound different),
  
• Data correlated jitter (jitter arising when certain patterns of data is present),
  
• Intrinsic jitter of receiver chips (that decode incoming SPDIF or AES digital signals).

These all affect audio quality (and potentially cause sync lock issues). What matters is that jitter is accumulative. This means all jitter sources combine in sometimes very harmful ways causing jitter gain (increase in Jpp).

Ultimately, all this jitter collectively affects the sample clock at the DAC or ADC chip. It’s at this sample clock level where signal conversion occurs that distortion arises (signal amplitude errors).

Clock jitter at the sample clock (LRCK) is most detrimental to DACs (and ADCs). DAC chips utilize multiple clock signals. Here’s AKM’s AK4358VQ (as used on the Juli@ soundcard).

Figure 3. Pin layout of AKM DAC chip that offers 8 output channels (4 LR pairs), digital data input (at bit level) is from pins 13-16. Clock pins are 17 (LRCK), 10 (MCLK) & 9 (BICK). AKM calls MCLK the Master Clock which is synchronized to LRCK (the most important and often referred to as sample or word clock). AKM uses MCLK to operate its interpolation filter and delta/sigma modulator. Ignore DSD pins.

Figure 4. Clock signals (PCM default mode) for AKM DAC chip. LRCK (sample clock) where 1 cycle is 1/Fs. BICK is the bit level clock similar to an SPDIF signal, for 24/96 BICK operates at 6.144mHz.

The sample clock determines when the sample (left and right pair) is dispatched at the desired voltage level for that specific moment in time. Timing errors here results in signal amplitudes out of time. Thus at the actual intended timing point, we have signal amplitude error. This is jitter distortion.

What’s very important to understand is that jitter is rarely random, it’s almost always periodic, ie. the worst kind. Phase Locked Loops (PLLs) are excellent at removing such periodic jitter. No matter the system configuration (i.e. single box, transport/dac, etc.) PLLs are hard at work removing jitter. Unfortunately, PLLs only do so after a defined ‘cut-off’ frequency which is often 1kHz. Any jitter below this cut-off frequency is not removed. One could argue that designs should move towards shifting jitter energy to high frequencies thus PLLs at the DAC’s sample clock effectively removes jitter. Unfortunately, such high frequency jitter comes with aliases and images of its own that occurs well below the cut-off.


Jittter Analysis
Jitter is almost always periodic in occurrence. Fortunately, for a given input tone (pure sine wave), this type of jitter can be modeled. But first, it’s important to understand what exactly periodic jitter is. The best way is to think of a tiny virtual clock oscillator beavering away at the DAC’s sample clock. This tiny oscillator is constantly changing the sample clocks timing accuracy (phase or edge error) – the actual clock phase is shifted by a small amount in time (ie. jitter error). This jitter error is given by:

J(t) = 0.5 Jpp Sin( Jf 2 Pi t)

Where:

J is jitter error in seconds applied to the sample clock phase,
t is the actual time for the clock phase,
Jpp is the peak to peak jitter,
Jf is the jitter frequency, and
Pi is the mathematical constant 3.141593…

In simple English, this formula says, the sample clock jitter (or phase error) is cyclical and at its worst would be half of Jpp (either adding to or subtracting from the clock phase). Over a full jitter cycle, the sample clock maintains perfect accuracy, ie. there are clock phases where the clock signal takes longer followed by shorter intervals. This is the nature of the Sin math function. Thus:

1. Given Jpp and Jf, we can determine the sample clock timing error for any sampling period (1/Fs).
   
2. For a given input sine wave tone, each sample’s signal amplitude (for any Fs) can be calculated.
   
3. Jitter distortion (erroneous signal amplitude) can also be calculated. At sample time t, the signal amplitude is what it should have been less the timing error. That is: v’(t) = v(t – J(t)), where v’ is the distorted signal amplitude.

Dunn provides the mathematical formula for modeling this jitter distortion of given Jpp and Jf when applied to an input sine wave tone. A utility, cicsTone is used to generate a wav file that implements this formula. cicsTone provides both pure tones (at either 16 or 24 bits at any Fs) and tones afflicted with periodic jitter. Very basic dithering and 3rd order noise shaping is applied – nothing sophisticated here at all. cicsTone will be available as usual in source and executable format at SourceForge.

Here’s a spectrum view of a 24/96 10kHz generated tone with jitter modeled at 7ns / 3kHz:

Figure 5. Compare this to figure 1 which is an actual live 10kHz tone having the same jitter. The model prediction is perfect with sidebands 3kHz apart (7 & 13 kHz) and of similar levels. Note frequency is in log scale. Spectrum is viewed using RMAA spectrum analyzer with FFT resolution of 0.37Hz.

This means that by recording the analogue outputs of the DAC for a given tone, jitter artifacts can be determined. The level & distance of the sidebands will provide exact Jpp and Jf measures for the Transport and DAC combination! Jf is taken from the spectral view whilst Jpp is calculated from the sideband level and using the formula in figure 2 (ie. solve for Jpp).

Using cicsTone, 3 generated test wav files are used:

Figure 6. Generated 24/96 wav files for measuring jitter. From left: 7kHz, 3kHz and 14kHz with simulated jitter at 7ns / 3kHz. The 14kHz test is to see the 3 tones (11, 14 & 17kHz) being recreated at the DAC’s output, ie. if this excessive jitter distortion was introduced by the ADC, it must be visible at the DAC’s output.

This type of analysis provides insights into the total jitter for both Transport and DAC. Things like the effectiveness of the DAC’s ability to reject incoming jitter (from Transport’s digital signal), complexities of interface jitter (and the use of high quality glass fibre toslink) and so forth is given by this overall measure. The need for Eye diagram analysis and other clock signal analyzing methods are done away with.



Jitter Measurement
cMP as Transport using RME’s HDSP 9652 soundcard feeding (24/96 via glass fibre toslink) to dCS Scarlatti DAC is measured. cMP provides master clock to DAC, ie. DAC is slaved to Transport.

Analogue outputs are recorded using a second cMP with some optimizations removed to cater for Steinberg’s Cubase LE recording software. Soundcard is ESI’s Juli@. The recording cMP also enjoys high quality power supply together with quality power cord and line filtration. Scarlatti’s balanced outputs are connected with high quality low capacitance interconnects at 25pF (Sommer Cable). XLR output from DAC connects to Juli@’s TRS analogue inputs. Cubase is set for recording stereo at 24/96.

This cMP recorder as a DSO offers 24 bit resolution with 384kHz bandwidth – for perfect measurements, high resolution with very high bandwidth DSOs are best.

Testing included the analogue outputs of a normal computer (Realtek ALC888 offering SNR of 97db), the recording cMP proved to be brilliant – showing all kinds of artifacts and noise. This was expected given that the normal computer is setup for high performance and not audio.


The recorded output from Scarlatti’s DAC using the 7kHz test tone is shown in figures 7 & 8.

Figure 7. Scarlatti DAC analogue outputs. Overall noise floor is at ~-136db with harmonics of the 7kHz fundamental at 14, 21, 28 & 35kHz. Noise in lower frequency bands (to just over 3kHz) is due to Scarlatti’s filter (set to filter 3).

Figure 8. Same as figure 7 but Scarlatti DAC filter set to filter 2 – preferred setting (although with some CDs, filter 3 is preferred). Note filter artifacts now move to the higher frequency band between 16 &18kHz). Same harmonics are visible. Noise floor drops to below -140db! THD is same at ~0.00039%.

What is cleanly seen from figures 7 & 8 after accounting for harmonic distortion and filter artifacts is the jitter component. For the 7kHz input tone, jitter sidebands are visible at exactly 2kHz away from the fundamental and correspond to a level of -122db. This gives a Jf of 2kHz and Jpp of just ~72ps!

Figure 9. Jitter is consistent with that seen in figures 7 & 8 with exactly 2kHz sidebands from fundamental. For 3kHz tone, sideband level is at -129db (1 & 5kHz). For 14kHz, same sidebands (seen between input side tones of 11 & 17kHz) are at -116db (12 & 16kHz). These levels correspond to the same Jpp of ~72ps. Remember, jitter sideband levels increase as input frequency increases. Recorded distortion is recreated at the DAC’s ouput (14kHz view showing 11 & 17kHz).

Both 3kHz (pure) & 14kHz (with side tones of 11 & 17kHz) resulted with exactly the same Jpp measurements (figure 9). This consistency is important to confirm such excellent jitter performance.


Conclusion
The greatest insight from this research and measurement is that jitter problems cannot be resolved by ‘polishing’ the sample clock. Clock polishing is treating the symptom and not the underlying cause. There’s no doubt the Scarlatti Clock offers amazing clock accuracy and low jitter. But XOs are achieving great levels of performance (ito accuracy and more importantly, low jitter ~20ps). Other factors like power supply noise act to destabilize XOs and consequently result in very poor jitter performance. A traditional transport based on spinning CDs will act to drastically destabilize the clock – in such cases, clock treatments as advocated by dCS are needed. This however does not hold true for Computer Transports.

What matters in design are the underlying causes. Power supply is well known and has seen amazing treatments. There’s much more. Figure 3 shows a typical DAC chip (this also holds true for proprietary DACs as similar inputs are required to perform its function). The seemingly perfect sample clock (after exhaustive treatment) entering the DAC chip would still be subject to noise ‘riding’ on other inputs. At a microscopic level, DAC chips are complex integrated circuits. The sample clock signal is NOT galvanically isolated. Hence noise pollution from data pins and other clock pins will no doubt impact negatively on the sample clock causing jitter. With DACs becoming ever more complex with even larger levels of sample buffering, this type of contamination is certain to grow. In other words, all pins need polishing. In a Computer Transport, things like RAM settings, its quality, mobo traffic etc. make a difference. The purity with which samples are streamed to the DAC is a big deal. This is where cMP excels.

From listening experience, jitter seemed very low. Never did I think Jpp of 72ps had been achieved! It makes perfect sense why the Scarlatti Clock failed to impress. The added complexity by way of an extra power supply, clock sync circuitry and loss of galvanic isolation adds more noise that eventually makes its way to the DAC’s sample clock. On the other hand, the Scarlatti DAC certainly impresses.

• Paper in pdf format (196KB)   (Open in New Window)

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