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RE: Jitter Research, Analysis & Measurement

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Thanks for extracting the relevant bits. I'm familiar with TNT's documentation. A DAC acting as master will still have:

  1. Loss of galvanic isolation
  2. Clock circuitry from DAC's XO to deliver signal
  3. Interface issues (transmission circuit, cable, BNC interface, signal coupling / noise rejection,...)


My learnings suggest that even with an XO placed at the DAC chip and assuming the clock signal going into the DAC chip is clean, contamination occurs. Think about these questions:
  1. What's inside the DAC chip?
  2. Why stop just at the chip's clock input?
  3. What happens with all the other (untreated) signals entering the DAC?

All these additional inputs have an impact on the sample clock. There's an assumption that the sample clock remains pure within the chip. My understanding of chips suggest this assumption is incorrect. Chips internally carry tiny sample buffers, have all kinds of logic circuits to perform filtration, upsampling and so on... This complex circuit is still subject to noise entering it. That pure sample clock does not act in isolation as it is integrated and therefore susceptible to noise.

Anyway, I also plan to measure this scenario (DAC provides master clock to Transport at 88.2k). Yes clock works in multiples of master, ie. 48 will also do 96 and 192 (same applies with 44.1).

RME jitter specs of < 1ns is a guide. Its difficult for manufacturers to provide exact jitter as they have no control over PSU quality and complexity of computer environment. These factors and more destabilize the XO which by itself is actually very good (~20ps).






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