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In Reply to: RE: Jitter Research, Analysis & Measurement posted by cics on March 25, 2008 at 13:06:53
I cannot figure out what the heck you are talking about here.
D/A converters have four signals typically, called I2S, including:
MCLK
SCLK
SDATA
L/RCLK
Most D/A chips do the conversion on the Bit clock (SCLK) or the Master Clock (MCLK). Depends on the chip which one. The quote from the SD guy says they are all Master Clock, but this is not true. Depends on the chip.
If you lower the jitter on the SCLK, you will have succeeded in lowering the jitter in the analog output for most D/A chips.
If the Master Clock is generated inside the DAC (very rare), and then divided-down to a word-clock which is output to the source device for synchronization, this is the optimum solution. The jitter on the Word-clock to the source device does not matter, as long as its not so bad as to cause errors. This is only necessary to get clean data image into the input FIFO. Once in the FIFO, the output clock is the one with ultra-low jitter. It takes a memory-based system to do this effectively.
The same thing can be done with a memory-based reclocker that sources the master or word clock to the source device, such as the Transporter. The reclocker can then drive all four signals of I2S to an I2S input DAC. This will acheive very low system jitter. Again, the jitter in the clock that is transmitted back to the source (as slave) is a "dont-care". Such reclockers work extremely well, even though they are a "third" box in the chain.
Steve N.
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