[
Top of Page ]
[ Contact Us ]
[ Support/Wish List ]
[ Copyright © 2008, Audio Asylum, all rights reserved ]
[ General ] [ Speakers ] [ Tubes ] [ Vinyl ] [ Digital ] [ Hi-Rez ] [ Video Asylum ] [ Cables ] [ Tweaks/DIY ] [ Music ] [ Films ]
198.54.202.234
In Reply to: RE: Jitter Research, Analysis & Measurement posted by audioengr on March 25, 2008 at 13:38:43
If you lower the jitter on the SCLK, you will have succeeded in lowering the jitter in the analog output for most D/A chips.
I'm not disputing this. You're also correct in that the clock treatment must be on the correct clock input signal (as this varies by manufacturer). Lets call this correct clock signal the master clock.
So, what am I saying then:
- Remaining clock signals entering the chip will carry jitter which is not directly related to the master clock jitter. Of course if these are are grossly jittered other issues arise. My understanding is that for these non critical clocks, level detection is used (as opposed to phase).
- Both the clock and data inputs however carry noise. This noise infiltrates the chip. Noise as mentioned before includes EMI (as in induced currents), RF pickup (into GHz), IMD, signal reflections and thermal noise. Remaining clock signals have jitter which I see as phase noise and this adds to the overall noise contamination.
- If chips are free from such contamination entering it, then yes only the master clock signal needs treatment. This is a large assumption.
Why regard the chip as a 'perfect black box' when in fact its a (very complex) circuit? There's bound to be interference at the master clock signal which entered the chip uncontaminated. This interference manifests as jitter.
Follow Ups:
Top of Page ]
[ Contact Us ]
[ Support/Wish List ]
[ Copyright © 2008, Audio Asylum, all rights reserved ]