196.11.134.77
In Reply to: RE: Jpp for DAC as Master (using 24/88.2) yields an additonal 4ps of Jitter posted by Sunya on March 31, 2008 at 22:30:06
Did you made all the necessary modifications in the control software of the RME to put it on Slave?
Yes.Also, did you terminate to 75 Ohm the WC input on the RME?
Yes.
Other points:
When I measure with RME as master, Clock card is disconnected from main PCI card. It's not good enough to just disconnect the BNC cable.
You cannot have both dCS and RME as Master - you hear abnormal click sounds.
Follow Ups:
- RE: RME setup - Sunya 01:24:40 04/01/08 (8)
- RE: RME setup - cics 01:46:19 04/03/08 (3)
- RE: RME setup - Sunya 02:42:48 04/03/08 (2)
- RE: RME setup - cics 05:20:20 04/03/08 (1)
- RE: RME setup - Sunya 06:56:12 04/03/08 (0)
- When RME is master, clock is embedded in SPDIF output signal - cics 02:01:12 04/01/08 (3)
- RE: When RME is master, clock is embedded in SPDIF output signal - Sunya 03:00:42 04/01/08 (2)
- RE: When RME is master, clock is embedded in SPDIF output signal - cics 08:43:07 04/01/08 (1)
- RE: When RME is master, clock is embedded in SPDIF output signal - Sunya 09:31:29 04/01/08 (0)
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