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In Reply to: RE: Jitter Research, Analysis & Measurement posted by cics on March 24, 2008 at 12:55:55
"Clock jitter at the sample clock (LRCK) is most detrimental to DACs (and ADCs)."
I have not found this to be true at all, in fact most D/A converter chip datasheets actually say that the conversion occurs on either the SCLK (bit clock) or the MCLK (master clock), not the word-clock. This is a common misconception.
"Hence noise pollution from data pins and other clock pins will no doubt impact negatively on the sample clock causing jitter."
So-called "noise-pollution" and "RFI" etc. are all words that describe phenomenon that are widely misunderstood. These are usually ground-loops causing "ground-bounce" or they are simply crosstalk or power supply noise.
Reducing jitter in all of the I2S clocks will achieve low jitter in the resultant conversion. I'm not sure I understand what you are saying in your conclusion. There are certainly a lot of sources of jitter in the typical digital streaming logic chain. In your case, you evidently had a mixture of ground-loop noise and jitter, and a miriad of different devices, probably all with non-ideal S/PDIF and clock interfaces. Do you know if the clock cables were impedance matched and properly terminated?
It reads that you are comparing a Transport DAC combination to RME and Juli@t PCI boards, and the RME board was slaved to the external Scarlatti Clock? Is this correct?
Steve N.
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