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In Reply to: RE: Jitter Research, Analysis & Measurement posted by cics on March 25, 2008 at 05:51:38
The RME jitter specification is quoted to be <1ns; I can't imagine it providing a better clock and sounding better in master mode than slaved to the Scarlatti DAC. Why not slave it at 44.1k, disable the SRC and let the DAC make any upsampling?Here are a few quotes form the founder of SD from the thread I gave the link in case you didn't had time to read it:
Quote:
Yes it is a manual setting. Please, notice that I use a DAC and en external clock, i.e. two units.?!? Why?
Such a configuration should only be used if you have some requirement to synchronize multiple _source_ components, perhaps for editing purposes.
It is the MCLK (eg 11.2896MHZ) signal that actually drives the internal operation of a modern DAC chip, and the whole point of word clocking (for the purpose of reducing jitter) is to put that clock as close as possible to the DAC chip itself.
A PLL is absolutely _terrible_ at generating a master clock from a word clock, compared to generating it directly with a crystal. But that is not even the only source of jitter - you are also accumulating it in all the connections between this equipment, and in the clock source device itself, as it has to divide a crystal-generated clock internally to produce that low word clock frequency.
I am not aware of any situation where a word clock would be advisable for driving a DAC. You will get jitter much worse than anything you'd get even from traditional s/pdif master->slave clocking.... i.e. this is not only defeating the jitter eliminating mechanism of the word clock interface, but is actually making the jitter far worse even than plain s/pdif. You are probably running your DAC on a few hundred picoseconds of jitter, as opposed to the 30ps or less that would come from a good quality internal oscillator.
Quote:
2) Even better is to syncronize both the DAC and the Transporter to an external clock - if this clock is of higher precision than the one in the DAC.No, this is where you are very wrong. I have already explained why from a theoretical standpoint, but to put it another way, which do you expect will have more jitter:
- A crystal oscillator running at 12.2880 MH, directly driving the DAC
Or
- A crystal oscillator running at 12.2880 MHz
- driving either a synchronous counter or a series of flip-flops, to divide that signal down to 48 KHz
- then feeding this signal through some transmission circuit to a BNC connector
- coupling that signal into a cable
- feeding it down the cable
- getting it into another connector at the other end of that cable
- driving that signal into a PLL circuit which multiplies the word clock signal back up to 12.2880 Mhz
- feeding the output of that PLL into the DAC chip.
Quote:
Finally, I still can not understand your theory of internal vs external clock (high precision oscillator) for a DAC. Please, notice that both Esoteric and dCS promotes this idea - and for me it works well with the Transporter and 44.1kHz.Which part of it is unclear?
Consider an absolutely perfect clock with zero jitter. No such thing exists, but let's just suppose for the sake of argument that your external clock source is such a device.
Now, divide that clock signal down to word clock speed (/128 or /256), send it through a bunch of cables and connectors, through a PLL to multiply it back up to MCLK speed, and then across another circuit board to the DAC chip. How can that possibly still be a clean clock? How could it possibly be cleaner than if you placed the crystal oscillator right next to the DAC chip? It can not. Not by any stretch of the imagination, and not even if you consider a _perfect_ external clock source compared to the poorest imaginable local crystal clock source. It is not even close. The external clocking scheme is worse by about a factor of ten. In practice you would get about 15-50ps for the internal clock, versus 100-300ps for the external, PLL-recovered clock.
The fundamental principle of word clocking, when used for the purpose of reducing jitter, is that you are eliminating all the crap between the clock source and the DAC. This is where jitter comes from. The quality of the crystal oscillator is actually not even a major factor.
Finally ask yourself, if dCS can produce a better clock signal through such a convoluted means, why would they not then simply build this technology into their $18K(?) DAC? Maybe they just want to sell you yet another overpriced box.
Look, I am not making this up and I have nothing more to sell you. What I am telling you is all solid theory that can easily be tested with suitable equipment. Have a look at this (and also be sure to jump back to part 1 for the introduction):
http://www.tnt-audio.com/clinica/diginterf2_e.html
What you need to do is shown in the "clock backwards" configuration. This is ideal - it puts the oscillator right at the DAC so that the clock signal does not flow through PLLs, dividers, or interconnects.
If anywhere in my reasoning you have found a mistake, please point it out and we can discuss. Otherwise it's pretty silly to just not believe me because my conclusions conflict with what the high priced stereo vendors have told you. There are guys who will sell you lacquered knobs and granite isolation plates too.
Edits: 03/25/08Follow Ups:
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