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In Reply to: RE: Do you mean ASRC's? posted by Scrith on March 27, 2008 at 02:15:49
This concept is similar to DAC as clock master architectures. These approaches still have unwanted jitter distortion.
DAC's local clock will have timing errors that displaces samples in time. Such large buffers will add to DAC's complexity and has the potential to make it worse.
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