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In Reply to: RE: Jitter Research, Analysis & Measurement posted by cics on March 25, 2008 at 22:48:01
"Remaining clock signals entering the chip will carry jitter which is not directly related to the master clock jitter. Of course if these are are grossly jittered other issues arise. My understanding is that for these non critical clocks, level detection is used (as opposed to phase)."
There is only one synchronous clock used on a DAC chip. The others are not effectively clocks. Sometimes the MCLK is used to do digital filtering, but does not affect conversion, which is where the jitter becomes audible.
"Both the clock and data inputs however carry noise. This noise infiltrates the chip. Noise as mentioned before includes EMI (as in induced currents), RF pickup (into GHz), IMD, signal reflections and thermal noise. Remaining clock signals have jitter which I see as phase noise and this adds to the overall noise contamination."
No, only the single clock signal matters. Once the data is clocked into the first flip-flop in the D/A converter, only the clock matters.
"If chips are free from such contamination entering it, then yes only the master clock signal needs treatment. This is a large assumption."
The data can be jittering a lot, but it does not matter. Only the clock matters. This is fundamental synchronous logic. Contamination means nothing. There is no such electrical phenomenon as "contamination", except maybe in water sources or air etc.. It is either timing jitter, ground-bounce or crosstalk.
Steve N.
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