Computer Audio Asylum

Jpp for DAC as Master (using 24/88.2) yields an additonal 4ps of Jitter

196.11.134.77

In Reply to: RE: Jitter Research, Analysis & Measurement posted by cics on March 24, 2008 at 12:55:55

I wanted to measure the setup with Scarlatti DAC as master and RME as slave. Clock connection from DAC's clock out is made to RME. Clock operates at 44.1k. Test wav file at 14kHz 24/88.2 is used.

Spectral analysis is very similar with 2kHz jitter sidebands having ~0.5db increase in level. This corresponds to Jpp of 76ps.

Setting DAC to slave mode gives Jpp of 72ps.

Follow Ups:

RE: Jpp for DAC as Master (using 24/88.2) yields an additonal 4ps of Jitter - Sunya 23:28:16 03/31/08 (8)
- Measuring accuracy - Jpp would be lower - cics 01:54:43 04/01/08 (7)
  - RE: Measuring accuracy - Jpp would be lower - Tony Lauck 11:54:18 04/02/08 (4)
    - RE: Measuring accuracy - Jpp would be lower - cics 01:24:30 04/03/08 (3)
      - RE: Measuring accuracy - Jpp would be lower - Tony Lauck 05:38:15 04/03/08 (2)
        
        RE: Measuring accuracy - Jpp would be lower - cics 10:53:03 04/03/08 (1)
        
        RE: Measuring accuracy - Jpp would be lower - Tony Lauck 14:33:06 04/03/08 (0)
  - RE: Measuring accuracy - Jpp would be lower - Sunya 03:18:08 04/01/08 (1)
    - RE: Measuring accuracy - Jpp would be lower - cics 08:38:38 04/01/08 (0)
RE: Jpp for DAC as Master (using 24/88.2) yields an additonal 4ps of Jitter - Sunya 22:30:06 03/31/08 (10)
- RME setup - cics 01:16:59 04/01/08 (9)
  - RE: RME setup - Sunya 01:24:40 04/01/08 (8)
    - RE: RME setup - cics 01:46:19 04/03/08 (3)
      - RE: RME setup - Sunya 02:42:48 04/03/08 (2)
        
        RE: RME setup - cics 05:20:20 04/03/08 (1)
        
        RE: RME setup - Sunya 06:56:12 04/03/08 (0)
    - When RME is master, clock is embedded in SPDIF output signal - cics 02:01:12 04/01/08 (3)
      - RE: When RME is master, clock is embedded in SPDIF output signal - Sunya 03:00:42 04/01/08 (2)
        
        RE: When RME is master, clock is embedded in SPDIF output signal - cics 08:43:07 04/01/08 (1)
        
        RE: When RME is master, clock is embedded in SPDIF output signal - Sunya 09:31:29 04/01/08 (0)

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