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RE: Thanks for the good wishes.

It's your project and it's for you to say what it's goals are and whether or not they have been (adequately) met. All and all, I think you've done a great job and provided an inspiration to many as to what can be done in a DIY project. Thanks for taking the time and effort to post about your project and putting up with the various flac that has been returned. :-)

There is one point where I personally would have slightly different goals had it been my project, so if you don't mind I'd like to clarify one point.

".) Some said (and still say) that a proper FIFO is sufficient to get rid of jitter. Once again that's obviously false to me but obviously true to the bits-is-bits people. I defy anyone to find a fault in my FIFO implementations or to build a FIFO that works gets rid of all audible effects of jitter."

A proper FIFO is necessary to get rid of jitter. It won't be sufficient, as there can be other jitter coupling modes, e.g. power used by input decoding stages can couple through power and ground into output clock circuitry. In addition, a FIFO may work perfectly at moving bits, but fail to achieve jitter isolation. Such a FIFO will be suitable for some applications, e.g. a buffer in computer interface, but not suitable to achieve jitter isolation in a DAC. Each component in the DAC FIFO needs to be modeled in the analog domain and the jitter attenuation of the FIFO as a whole needs to be modeled and verified empirically. Until this has been done it's not possible to conclude that a given FIFO is "proper" for the DAC application. I suspect there are many FIFO architectures that work satisfactorily for pumping bits that fail to achieve additional jitter attenuation when cascaded. This will depend on the circuit design, layout and, especially, the clock architecture. There aren't a lot of components (e.g. transistors) in some FIFO designs, so it would seem possible to design in such a way that each stage of the FIFO provides a constant (dB) attenuation of jitter. It looks to me like you've got most of the tools at hand to investigate this aspect of the design, should you decide to do so at some point in the future. However, if your FIFO is in the FPGA there may be no way to achieve sufficient isolation, due to the design of the cells and/or the available wiring.

It won't be possible to get perfect isolation, nor is it necessary. The effect of jitter is to introduce noise modulation onto the output analog signal, and if you can get this noise modulation well below the output noise of the DAC itself that will be sufficient. Modeling and measuring the jitter related output noise caused by the available degree of isolation won't be easy, but it can be done and must be done if one wants to solve this problem.

It is also possible that the audible effects of changing the transport have nothing to do with jitter, or even to do with the DAC. There could be other modes of coupling (e.g. RFI/EMI) to the downstream analog components. There are probably experiments that can be devised to evaluate these coupling modes.

The only other part of your discussion that I could possibly disagree with concerns power cords. But I'm not really interested in power cords, since all the evidence seems to indicate that the effect of power cords depends on all the components in the system and the general electrical environment. If I were a fanatic about power cords, I would just get rid of them completely e.g. run my components on internal batteries. :-)

Tony Lauck

"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar


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