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RE: Thanks

I'm doing something very similar to Ted, I'm using the smallest FPGA that Altera makes and can easily do a 1K FIR with 58 bits internal precision.

I think the issue was using FPGAs with builtin DSP "cores", you had to live with their bit limitations. But for a simple thing like an FIR you can just use the normal gates and use whatever bit depth you want.

Ted brings up an interesting point about coefficient optimization, thats something that rarely gets discussed and can be very important. Building the whole thing out of just the random gates lets you do strange things like use 28 bit coefficients.

John S.


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  • RE: Thanks - John Swenson 17:36:20 10/28/10 (1)

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