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RE: Two questions...

Howdy

I first have two 2:1 upsampling filters which are optionally bypassed depending on whether the PCM rate is above 48 or 96. Then I have a 160 or 147 times upsampler depending on 44.1-88.2-176.4 vs 48-96-192. A simple 5 times decimator gets me back to 5,644,800.

Then I use a fairly standard sigma delta quantizer of the dot product of coefficients and a series of 5 limited integrators variety.

Yep it's all in the FPGA so I can play with it. I'd done enough experimenting with quantizers in the past that I'm fairly happy with that part and also I'm pleased with the final PCM upsampler. But as I mentioned earilier I'm still thinking about the filters in the 2:1 upsamplers.

I can't keep noise from the clock from becoming jitter, but I can take steps to have as jitter free a clock and clock distribution as possible:

I had Vectron build me a VCO oscillator module that was similar to their best low freq phase noise spec module but with a 200 ppm pull and a 8 Fs rate - 22,579,200Hz. I control the frequency with a SPI controlled R2R ladder. There are 2k serial resistors in the control lines for the SPI signals to lessen bleed thru from the processor. I filter the resultant frequency control signal to further lessen any bleed thru from upstream. I then filter the crap out of the power supply for the oscillator and separately the other power supply for the R2R DAC and its low pass output filter. These power supplies are on a separate AC transformer from the ECL/CMOS transformer or the left analog or right analog transformers.

Further I only change the output frequency as rarely as possible: never more often than once a second and perhaps not for a minute or two if we get lucky and the clocks are very well aligned.

The Vectron chip outputs CMOS so I immediately convert that to differential ECL with a quality high speed ECL one in two out clock buffering chip. I use controlled impedance differential traces for all ECL signals with appropriate termination in or near the destination chips. I use two fully differential ECL D-flip flops in series which reclock the output DSD signals from the FPGA. One differential ECL clock signal goes to the FPGA, the other to the second of the flip-flops. (The first flip flop is clocked by the FPGA.)

All of the ECL parts have random RMS jitter specs of 0.2ps or better. For each ECL chip I use a local power island with its own local ferrite bead, storage cap and bypass caps.

Here's the clock module, the ECL clock splitter and the 2nd flip-flop with associated bypassing, etc.:





-Ted


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