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RE: Following on from Tony's suggestion ...

Howdy

Yep we've been here before: But this time I have some specific examples which might clarify things.

There is more compute power in a small FPGA than the host computer (by far) and one can precisely control the precision and accuracy at each step of the game.

For example a 44.1 to 88.2 upsampling filter could use 62 bit fixed point accumulators because that's what it would need based on the input precision (in this case 24 bits), the coefficient precision (in this case 28 bits) and the number of taps (approx 2000 for this example). This gives an exact result assuming the coefficients are completely accurate. But even that is easily controlled. For this example I chose 28 bit coefficient just so that after quantization (and normalization) of them from the theoretical real values to fixed point I'd have an acceptable pass band and stop band:





Then after the each output sample is summed we know by construction that 24 bits is necessary and sufficient to represent the same accuracy as the input: use more bits on the bottom if you want some "guard" bits. To be a little more precise I choose to have one extra bit on the top for our buddy Gibbs and 3 extra bits on the bottom beyond the 20 needed for 120dB S/N so I use a 24 bit data path between high level blocks allowing easy dynamic bypassing of various filters...

The size of all intermediate results for the next two upsamplers are different and 61 bits for the volume control before the general SD quantizer and then 30 bits in the limited integrators proper (after all they are limited by design :) The dot product of the integrators and their coefficient before the quantizer proper doesn't need near this much accuracy, it's inside the feedback loop and errors are automatically corrected.

I'm even a little more profligate with my precision and math since I'm in favor of simpler and more conservative code (less bugs) as a valid trade off if the design fits in the FPGA and runs in real time.

-Ted


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