In Reply to: RE: Following on from Tony's suggestion ... posted by Ted Smith on October 25, 2010 at 16:58:38:
I didn't think that FPGA would have sufficient real estate for the intermediate computational accuracy that you've strived for, so thanks for the clarification.
Past implementations I have been have limited intermediate computational accuracy to 48 bits (or even worse, 24!).
My experience with FPGA dates from nearly 20 years ago - I should have realised things have changed :-)
I do agree that if you can fit it all in the FPGA and it's real time that's a lot better than chewing up host CPU cycles.
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Follow Ups
- Thanks - Christine Tham 17:25:45 10/25/10 (2)
- RE: Thanks - John Swenson 17:36:20 10/28/10 (1)
- RE: Thanks - PET-240 18:25:23 02/21/13 (0)