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My new DAC (long, but with pictures)

71.121.200.218

Posted on October 24, 2010 at 16:45:50
Ted Smith
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Howdy all

It's been a while since I posted at the Asylum so I thought I might update you all on what I've been doing:

I built a DAC:



My goal wasn't to build the most cost effective solution: I wanted to verify some ideas I had. If I built a no holds barred board and it didn't work I would know that I had failed fundamentally and not just because I chose cheap solutions.

The board is a monster:

Number of copper layers: 6
Board outline(s) extent: X = 455 MM; Y = 330 MM
Number of parts: 1471
Number of pins: 5284 (258 through-hole, 5026 SMT)
Number of vias: 3205
Number of holes: 3463

It's features are outlined below. But first some history:

A few years ago I thought I'd make a DSD based DAC and since I'm a software guy I started out by prototyping a quick and dirty output stage, just some passives filtering the raw DSD in an Sony DVP-S9000ES:



Then since I'd never built hardware before I cobbed a quick dual output power supply:



I simulated some of my ideas with the demo version of MicroCap 9 (http://www.spectrum-soft.com/index.shtm) and tho things looked good I didn't know what tools were available so I contracted a quick layout of my schematics:



The boards were daisy chainable and I had three built with differing output stage component selections. I could just use my preamp input selections to A/B/C the boards.

The boards sounded pretty good, but there was some "breathing" in the gaps between notes and the output level was much to low for most systems.

I found FreePCB (http://www.freepcb.com/) and figured out how to export my schematics from MicroCap and built my next board with better power supplies and a different DSD amplifier and a custom VCO from Vectron with 200ppm pull and DSD x 8 frequency:



It sounded like crap :) Too much aliasing, worse "breathing", more crunchy. Yuck!

Also the clock circuitry drew so little current that the voltage in the clock power supply floated too high:



After thinking for a while I surmised that I needed double rate DSD and more solid power supplies. After running some experiments to verify various hypotheses I laid out my current board using the following guidelines:

1) Clean power
2) Clean DSD switching
3) Clean clocking
4) Good isolation

I built better power supplies with lots of filtering. (There are 9 of them including 3 for the FPGA, left analog, right analog, 2 ECL and two for the clock.)

I used ECL for clean distribution of the DSD.

I kept the custom Vectron oscillator modules, but I added more filtering of the control signals and their own power supply.

The board is dual mono, balanced differential so there is essentially no chance for even order harmonic distortion and I selected my bypassing, etc. to keep the THD below the 120dB noise floor, at least in the simulations. I haven't had the chance to use something better than my PicoScope to look at distortion, but it shows no distortion withing it's noise floor from about 7Hz up to 20kHz (where I stopped looking.)

To assist in noise control I made sure everything was electrically isolated: output transformers, power supply transformers, AES/EBU and SPDIF transformers, optical connectors for TOSLink or Meitner ST glass DSD.

To save on popcorn logic and to allow easy processing of PCM to DSD I put on a Xilinx FPGA along with the MIPS MCU controlling processor. The FPGA also allows me to avoid other LSI chips like AES/EBU and S/PDIF receivers... No PLLs here :)

The board can process:
1) DSD hard wired (well thru a digital isolator)
2) DSD via Meitner orange ST glass
3) TOSLink
4) RCA S/PDIF
5) XLR AES/EBU

The PCM can be 44.1, 48, 88.2, 96, 176.4 or 192.

I synchronously upsample all PCM to 28,224,000 Hz then to double rate DSD (5,644,800 Hz) and also I upsample DSD to double rate DSD.

It's dynamic, "fast", easy to listen to, has a flat freq response and has no grit or jitter edginess.

The board with no case, just sitting on a cardboard box, and with no magic power cords or interconnects, etc. and using a USB to S/PDIF converter then a S/PDIF to TOSLink converter sounds better than my Meitner or anything else I've heard.

When I had my hypersensitive pregnant daughter A/Bing it vs. the Meitner DAC6e her body jerked each time I selected the Meitner and on about the fourth switch she said "Stop that" :)

A few more pictures:

The raw board:



The processor and FPGA (and lots of bypass)



Bring up of 2nd board:



Early FPGA dev with a Xilinx eval board:



-Ted

P.S. I still don't have enough time to read everything here, but I'll at least watch this post for a while and try not to be too cagey :)

 

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RE: My new DAC (long, but with pictures), posted on October 24, 2010 at 17:06:24
fmak
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Very well done!

 

Thanks. [nt], posted on October 24, 2010 at 18:02:14
Ted Smith
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RE: My new DAC (long, but with pictures), posted on October 24, 2010 at 18:58:13
alan m. kafton
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All I can say is WOW! That's a lot of work over a good period of time. Superb job, Ted.

 

RE: My new DAC (long, but with pictures), posted on October 24, 2010 at 19:06:58
Sunya
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Chord also uses a Xilinx Spartan 3 to do pretty much all the work in their DAC but they also employ a digital PLL for when you can't use the RAM buffer (delay of audio with video sources).

 

RE: My new DAC (long, but with pictures), posted on October 24, 2010 at 20:02:04
Ted Smith
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Howdy

But why use any PLL? All PLL's are, at best, low pass filters for jitter.

Oversampling, say, the S/PDIF input and ignoring the timing entirely gives much better input jitter rejection :) You don't need to measure the input freq at all, you just have to recover the data correctly and not overflow or underflow your local buffer (however big or small) while using as few and/or gentle local freq updates as possible.

A PLL tries too hard to follow the local vagaries of the input clock rate by following edges and essentially doesn't use any buffering at all. A FLL uses approx a one sample buffer and so allows for more jitter rejection. A general elastic buffer lets you trade off buffer size for jitter reduction in essentially a continuous manner avoiding having to have multiple algorithms.

Yep digital control is great, it allows virtually instantaneous "locking" while still dealing with a wide range of frequencies.

-Ted

 

RE: My new DAC (long, but with pictures), posted on October 24, 2010 at 20:19:13
Ted Smith
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Howdy again

(Before I got carried away) I meant to say that the Spartan 3s are nice FPGAs: good cost / cell, free tools and available in non BGA packages (this board was already complicated enough without dealing with BGAs :)

-Ted

 

Thanks., posted on October 24, 2010 at 20:22:33
Ted Smith
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Howdy

It's always fun learning new things :)

-Ted

 

Long time no hear :-), posted on October 24, 2010 at 20:37:03
Christine Tham
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Looks very impressive, I'm amazed that it beats the Meitner.

How do you find PCM listening on it?

 

RE: Long time no hear :-), posted on October 24, 2010 at 21:04:08
Ted Smith
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Howdy Christine

It has been a while, give me a buzz if you're back in town with some extra time on your hands :)

Well I haven't built a multichannel DAC yet so I'll keep the Meitner for a while :)

PCM at 24/88.2, 24/96 and higher is essentially the same as stereo DSD, EXCEPT perhaps for a little ghostlyness. By this I mean that it has the same soundstaging, freq response, quickness, ease, and other such features as DSD, with the exception that DSD is still a little more real sounding than PCM. At this point if I'd never heard stereo DSD I'd probably not miss it.

I still don't like a lot of 16/44.1 as much. It's great to listen to, but there's something more missing. Tho I'm quite happy with my 176.4 and 192 to double rate DSD upsampling filter I'm still playing with the 44.1 to 88.2 filter (which is also the 48 to 96 filter) and I'm not sure if there's anything more to extract from 44.1 with different/better filters or if I've reached it's limits (as far as my aging ears anyway.)

[edit] I should add that tho in the past I hated USB audio I'm quite happy with USB to my DAC. FWIW I run WinAmp w/ ASIO in the background and I can run 3 parallel FPGA compiles while doing other work (even including ripping CDs) and never miss a beat or even hear any difference compared to using the laptop for WinAmp exclusively. I guess it also helps that I don't care a hoot about timing, just get me the bits :) Still Windows 7 64-bit (finally) lets mear mortals do what we did under Windows 3.01 with custom hardware and device drivers back in the 80's :)

-Ted

 

RE: Long time no hear :-), posted on October 24, 2010 at 21:45:48
Christine Tham
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I'm probably going in the opposite direction (most of the music I listen to these days are MP3 -v2 ~190 kbps on cheap Sennheiser earbuds so in comparison 16/44.1 sounds like heaven)

I do miss DSD though. Unfortunately, my XA777ES haven't really worked properly for a few years now (it's been to the shop a few times, and they have replaced the laser, upgraded the firmware, replaced the DAC op amps, and I can't remember what else but it still doesn't play very well)

I now have a Oppo BDP-83SE NuForce Edition. I like the NuForce sound, but the PRaT is not as good as my custom music PC, and somehow the overall sound is a bit too overblown/larger than life for me. But for watching Blurays it's fine and the exaggeration kinda works :-)

I'm not a big fan of USB audio but have learnt to live with it since I'm still using my old Edirol SD-90 in my DAW. It's quite noisy (since it's a US model and the power supply does not filter the Aust 50 Hz artefacts very well) but for monitoring on headphones and sending to my powered monitors they seem fine.

I also bought an E-MU 0404 USB on my last trip to the States. The playback was a tad disappointing but the recording is fantastic - I have been using it to record my LPs at 24/96.

 

Hi Ted, did you have to drill the holes all by yourself, one by one?, posted on October 24, 2010 at 23:19:49
Chris Garrett
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Just kidding.

Glad you're still alive!

Chris



 

:), posted on October 25, 2010 at 00:43:16
Ted Smith
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Howdy

Yep, I still exist :)

The board house did say that they were glad that they'd just upgraded their drilling equipment: the boards would have caused significant wear on their older equipment (small holes thru 2oz copper on all layers, etc.)

-Ted

 

RE: Thanks. [nt]-I did it too, but, posted on October 25, 2010 at 02:30:29
fmak
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with a ESS Buffalo with pcm and dsd input from the board of a DV989 Universal player.

DSD sounds very good from SACD discs, perhaps more balanced than pcm 192k over the frequency range.

The analog roll off frequency is rather important and are the power supplies which in my case are 6 ALW feedback super regulators and a non feedback one for the clock. The system is all balanced direct coupled.

 

RE: Thanks. [nt]-I did it too, but, posted on October 25, 2010 at 04:20:35
Ted Smith
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I do like SACDs a lot, they just sound more real to me. I don't really detect any difference in the sense of balance (if I understand what you mean by balance :) But my opinion has changed quite a lot over the years as my system has gotten better. PCM no longer sucks :)

Also I really like the fact that "all" you have to do to build a DSD dac is to filter the DSD stream: no need for DAC chips, steep filters, word clocks, etc. In the abstract just a stream of bits into a simple analog filter and presto: great sound.

I'd spent a lot of time running C++ simulations of DSD years back and then again more recently in Spice and I agree that finding good reconstruction filters (especially when they are all passive analog) isn't easy. Here's a simulation run from about a year ago:



I looked at regulators similar to ALW's but since I was using all surface mount and needed a lot of current for the analog and FPGA I chose to implement each PS custom to its needs. Also I wanted to filter the crap out of the controlled voltage over a very wide frequency range (e.g. to above 50MegHz for the analog and clock supplies) and still have low output impedances where it counts:



Truth be told, when I thought I had a analog PS problem and was running the analog outputs from a dual bench supply the board still sounded pretty good. Having gobs of low impedance bypass at my DSD switching rate did most of the work :)

-Ted

 

Two questions..., posted on October 25, 2010 at 08:43:17
Tony Lauck
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How are you converting PCM to (double rate) DSD? There are a lot of different ways it can be done, e.g. different noise shaping filters. Is that something that you can easily experiment with?

Could you also say a bit about the clock oscillator and what you do to keep noise on the clock signal from turning into jitter on the output of the switch?

Tony Lauck

"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar

 

I'll ask the tough question, as I have no idea what those parts cost, but..., posted on October 25, 2010 at 09:48:28
Chris Garrett
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what did you spend building this project, since you contracted out and made various iterations? Forget your time, as this is hobbyesque for you.

$500, $1000, $4000?

I went back and reread your post, but a lot of it's Greek to me.

Chris




 

RE: Two questions..., posted on October 25, 2010 at 10:22:09
Ted Smith
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Joined: December 29, 2000
Howdy

I first have two 2:1 upsampling filters which are optionally bypassed depending on whether the PCM rate is above 48 or 96. Then I have a 160 or 147 times upsampler depending on 44.1-88.2-176.4 vs 48-96-192. A simple 5 times decimator gets me back to 5,644,800.

Then I use a fairly standard sigma delta quantizer of the dot product of coefficients and a series of 5 limited integrators variety.

Yep it's all in the FPGA so I can play with it. I'd done enough experimenting with quantizers in the past that I'm fairly happy with that part and also I'm pleased with the final PCM upsampler. But as I mentioned earilier I'm still thinking about the filters in the 2:1 upsamplers.

I can't keep noise from the clock from becoming jitter, but I can take steps to have as jitter free a clock and clock distribution as possible:

I had Vectron build me a VCO oscillator module that was similar to their best low freq phase noise spec module but with a 200 ppm pull and a 8 Fs rate - 22,579,200Hz. I control the frequency with a SPI controlled R2R ladder. There are 2k serial resistors in the control lines for the SPI signals to lessen bleed thru from the processor. I filter the resultant frequency control signal to further lessen any bleed thru from upstream. I then filter the crap out of the power supply for the oscillator and separately the other power supply for the R2R DAC and its low pass output filter. These power supplies are on a separate AC transformer from the ECL/CMOS transformer or the left analog or right analog transformers.

Further I only change the output frequency as rarely as possible: never more often than once a second and perhaps not for a minute or two if we get lucky and the clocks are very well aligned.

The Vectron chip outputs CMOS so I immediately convert that to differential ECL with a quality high speed ECL one in two out clock buffering chip. I use controlled impedance differential traces for all ECL signals with appropriate termination in or near the destination chips. I use two fully differential ECL D-flip flops in series which reclock the output DSD signals from the FPGA. One differential ECL clock signal goes to the FPGA, the other to the second of the flip-flops. (The first flip flop is clocked by the FPGA.)

All of the ECL parts have random RMS jitter specs of 0.2ps or better. For each ECL chip I use a local power island with its own local ferrite bead, storage cap and bypass caps.

Here's the clock module, the ECL clock splitter and the 2nd flip-flop with associated bypassing, etc.:





-Ted

 

I'll equivocate :), posted on October 25, 2010 at 10:32:04
Ted Smith
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Well the second board's parts cost was in the $ks and in addition the physical boards weren't cheap. Also the labor to build it cost $ks. The earlier boards were a little cheaper and as you mentioned contracting the first layout wasn't cheap either.

All in all I don't want to add it up :) But I consider it worth it: a lot cheaper than learning all of this at a college and it will make a great resume :)

-Ted

 

Hey, it looks like some software dude built that DAC. ;-), posted on October 25, 2010 at 10:33:27
AbeCollins
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Wow, very nice. SMT scares me and that board looks complicated! Nice.

 

You said it :), posted on October 25, 2010 at 10:39:16
Ted Smith
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One of the most valuable lessons I learned at a startup a long time ago was to balance software vs. hardware: to get higher speed we treated DRAM like a disk and selected RAS and CAS separately so we could read the DRAM about 10x than all of our competitors. We also did DRAM refresh in software :) These days the trade offs are quite different.

Still I'd have to agree with your comment :)

As to SMT: it's stinking great in every way except patching bugs. So I can't make hardware mistakes :) It helps that I've always been of the mind set that getting a compile error after a few days of entering new code was a "failure."

-Ted

 

RE: Two questions..., posted on October 25, 2010 at 11:05:14
Tony Lauck
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"But as I mentioned earilier I'm still thinking about the filters in the 2:1 upsamplers."

Not much you can do about that one, because the best solution will depend on the filter used in the original recording. I've found it convenient to explore this space by using the 64 bit Izotope SRC and doing file to file sample rate conversions. My inclination would leave this level of SRC to software in a PC, if this is convenient. My experience with upsampling (e.g. 44.1 to 176.4) most CDs is that best results are obtained with a minimum phase filter with moderate slope, set at 94% of Fs/2 and eliminating nearly all images by Fs/2. However, the recordings I've been making use a similar anti-alias filter to downsample to 44.1, and with these best results are had with a traditional half-band sinc filter (which really gives what's "on" the recording). Of course the variations in upper octave phase and amplitude are really subtle tone controls.

Did you consider going to even higher clock rates on the output, e.g. the actual Vertex clock rate, or would the computation in the modulator be too expensive?

Tony Lauck

"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar

 

RE: My new DAC (long, but with pictures), posted on October 25, 2010 at 11:30:24
rsub8a
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Beautiful layout... especially liked that closeup of the stripline traces...

 

RE: Two questions..., posted on October 25, 2010 at 12:03:00
Ted Smith
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I agree about minimum phase filters: I tend to use monotonic IIR's for the obvious reasons. Tho some may argue, I can deal with their vagaries pretty easily in the FPGA.

I'm using the Spartan 3E and I am using a variety of internal clocks as needed: 1Fs, 8Fs, 20Fs and 56Fs. My choices weren't limited by the FPGA but instead by the natural rates of the processes involved: e.g. 10Fs is the least common multiple of 192k and 176.4k so 20Fs (10Fs * 2 for left and right) is the clock rate I chose for that conversion... As I've currently implemented them the AES/EBU, etc. converters have to run at at-least 7 times the max raw bit rate, but there's little reason to run faster than that. (I also have a slightly less robust version similar the the Xilinx example code which only needs to run at four times the max bit rate.)

The SD quantizer isn't currently a bottle neck (tho it took some time to get it to that point.) Right now most of the real-estate and time is chewed up by the upsampling. (See below.)

As to output rates I had to match them with the physical analog filter (which I could have changed easily enough.) But the real limit is that as you go to higher clocks you get out of fundamental mode crystals and into 3rd overtone crystals which add to the clock phase noise. Further I have no evidence or expectation that oversampling to higher rates is worth it: my S/N, amplitude response, phase response and impulse response across the audio band in the 147 (or 160) upsampling filter is excellent so I don't "need" to use a gentler filter. Also at this point, truth be told, even doubling my output sampling rate would cause a lot more time / FPGA code iteration or I'd have to pick a different internal filter architecture. Right now it's a brute force single rate change upsampling filter, but it's only about 20 lines of Verilog :)

With the FPGA I have plenty of power to do whatever conversions I want on the fly, tho I'm adverse to providing too many options to the user. Before I got the board back I experimented with various conversions in C++ where I could model the varying precisions of floating and fixed point math in a potential FPGA algo. (I sure don't trust other people's coding of SSRC or ASRC.) Now that I have the board it's just as easy to experiment in real time with the FPGA.

If I choose to use a fixed filter I'm leaning towards a windowed sinc for 44.1 assuming that the only reason someone would have 44.1 these days is from legacy (CD) recordings that that's the best I can do in that case. But experimenting with various self adjusting filters is next on the todo list...

-Ted

 

RE: My new DAC (long, but with pictures), posted on October 25, 2010 at 12:23:20
Ted Smith
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Thanks, that's one of the things I mulled over staring at the wall until I was satisfied that the crystal to output flip flop path was as clean (and small) as I could get it. The other clock and data paths, tho still controlled impedance stripline, are less critical.

When I was pondering the board layer stackup I used various formulas to calculate the differential impedance of the striplines and magically I got 8 mil traces with 8 mil clearance which matched the design rules I was using anyway. When I talked to the board house it turned out that all of my assumptions were wrong but with their correct data they got a differential impedance of 99.09 ohms anyway :) When they did the TDR on the raw boards they came in at +/- 1.5% of this.

-Ted

 

RE: Two questions..., posted on October 25, 2010 at 14:38:53
Tony Lauck
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Interesting. It looks like you've spent a lot of time on this project and know what you are doing.

Do you have any noise spectra that you can post? I'd be curious to see what this approach is capable of when well executed.


Tony Lauck

"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar

 

Following on from Tony's suggestion ..., posted on October 25, 2010 at 15:09:18
Christine Tham
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Have you considered a hybrid HW/SW approach where the DAC only accepts double rate DSD, and the driver on the OS upsamples everything to double rate DSD?

You can probably take advantage of the higher processing power of the host. For example, on a music only PC you could dedicate both CPU cores to upsampling each channel :-)

I must admit I am not a big fan of FPGA filters - not a criticism of what you've done, just concerned about implementation trade offs compared to host based DSP. A conversation I know we've both had in the past.

 

RE: Two questions..., posted on October 25, 2010 at 15:37:03
Ted Smith
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Unfortunately the only relevant devices I have are a PicoScope 3206 (http://www.picotech.com/computer-oscilloscope.html) and various (relatively cheap) 24/96 or 24/192 A/Ds. The scope only has 8 bits precision @ 200MHz bandwidth (more precision if you do averaging) and the audio A/Ds only cover the audio range of frequencies. Neither really reach their theoretical accuracies, e.g. I still see noise with the ground wire directly clipped to the probe tip.

I do most of my debugging with simulations, ears, AM radios, A/D audio input recording, whatever I need that doesn't cost a fortune :)

On my previous boards even tho I had good isolation and noise rejection thru the DSD inputs I found noise in the 100's of MHz coming in via the power cord and also thru direct radiation from the open S9000ES, so I made sure that my new supplies have high input noise rejection and low output impedance over a wide frequency range. I can no longer hear differences when I use the S9000ES transport controls so I infer that I've moved in the right direction :)

When I run out of improvements I can make in software, etc. I'll see if I can borrow (or rent) some real test equipment.

I'm sure that many of the things I've done are way overkill and that I could get most all of the same quality of sound with a lot less hardware, but as I mentioned at the outset I didn't want to wonder what would happen if only I did this, that or the other thing.

Here is the data from the previous board. It will illustrate what the PicoScope can and can't do. I apologize for the fuzz, but I didn't want to post the 6Meg versions of the .jpgs. Also I apologize that the vertical scales can't be taken literally and that they have different horizontal scales: I captured these for my own debugging not for public consumption and didn't take care to normalize the results.

Here's the noise floor with the S9000ES stopped:




Here's the noise floor with the S9000ES spinning, but paused:




Here's the a similar plot but zoomed in:




-Ted

 

RE: My new DAC (long, but with pictures), posted on October 25, 2010 at 16:15:51
PaulN
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what a great project for you Ted! I'm envious. Makes me wish Id joined the Borg back when so I could retire and play with such toys too.

 

RE: Following on from Tony's suggestion ..., posted on October 25, 2010 at 16:58:38
Ted Smith
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Yep we've been here before: But this time I have some specific examples which might clarify things.

There is more compute power in a small FPGA than the host computer (by far) and one can precisely control the precision and accuracy at each step of the game.

For example a 44.1 to 88.2 upsampling filter could use 62 bit fixed point accumulators because that's what it would need based on the input precision (in this case 24 bits), the coefficient precision (in this case 28 bits) and the number of taps (approx 2000 for this example). This gives an exact result assuming the coefficients are completely accurate. But even that is easily controlled. For this example I chose 28 bit coefficient just so that after quantization (and normalization) of them from the theoretical real values to fixed point I'd have an acceptable pass band and stop band:





Then after the each output sample is summed we know by construction that 24 bits is necessary and sufficient to represent the same accuracy as the input: use more bits on the bottom if you want some "guard" bits. To be a little more precise I choose to have one extra bit on the top for our buddy Gibbs and 3 extra bits on the bottom beyond the 20 needed for 120dB S/N so I use a 24 bit data path between high level blocks allowing easy dynamic bypassing of various filters...

The size of all intermediate results for the next two upsamplers are different and 61 bits for the volume control before the general SD quantizer and then 30 bits in the limited integrators proper (after all they are limited by design :) The dot product of the integrators and their coefficient before the quantizer proper doesn't need near this much accuracy, it's inside the feedback loop and errors are automatically corrected.

I'm even a little more profligate with my precision and math since I'm in favor of simpler and more conservative code (less bugs) as a valid trade off if the design fits in the FPGA and runs in real time.

-Ted

 

:), posted on October 25, 2010 at 17:05:37
Ted Smith
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Just to be clear my retirement money (such as it is) isn't from the borg :) It's a long story but it amounts to the results of joining WaveFrame a company that I knew would fail but whose technology I believed in and wanted to work on. The lessons I learned there as well as the people I met allowed for a very interesting career before the borg.

-Ted

 

Thanks, posted on October 25, 2010 at 17:25:45
Christine Tham
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Location: Sydney
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I didn't think that FPGA would have sufficient real estate for the intermediate computational accuracy that you've strived for, so thanks for the clarification.

Past implementations I have been have limited intermediate computational accuracy to 48 bits (or even worse, 24!).

My experience with FPGA dates from nearly 20 years ago - I should have realised things have changed :-)

I do agree that if you can fit it all in the FPGA and it's real time that's a lot better than chewing up host CPU cycles.

 

RE: :), posted on October 25, 2010 at 17:28:36
Christine Tham
Reviewer

Posts: 4839
Location: Sydney
Joined: December 29, 2001
Just as well, because the Borg isn't looking as all-dominating as they used to be :-)

Are you still "retired"? Married life haven't sucked your finances dry? :-) [apologies for the cheap shot, and no insult intended to your beloved]

 

RE: Power Supplies, posted on October 25, 2010 at 19:08:20
fmak
Audiophile

Posts: 13158
Location: Kent
Joined: June 1, 2002
I used ALWs because they give very low levels of noise to at least 1 MHz (limit of my uV meter prior to roll off). Anything above, I filter with appropriate bypassess. A comparison of PSs on my system consistently favours Jung type regulators with pre-regulation over brute force ones.

However, the analog filtration (slope and fs) affects sound significantly.

By balance, I mean the relative emphasis of hf and lf notes, with dsd sounding 'smoother' overall and pcm providing more emphasis depending on material, ie DSD is 'easier' to listen to.

 

RE: Power Supplies, posted on October 25, 2010 at 21:31:33
Ted Smith
Manufacturer

Posts: 10297
Location: Seattle
Joined: December 29, 2000
Howdy

Yep, that's what I thought you meant by balance. As time goes on and my system gets better I find this to be less and less of an issue. Certainly with this DAC there isn't any balance issue with higher rate PCM. 44.1 still has something slightly missing but (at least with my current hearing) I don't perceive it as a balance issue.

-Ted

 

RE: :), posted on October 25, 2010 at 21:33:48
Ted Smith
Manufacturer

Posts: 10297
Location: Seattle
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Howdy

We're not too far from needing the IRAs... :) If I can't make some money with this board I can at least use it for a resume :)

=Ted

 

Oh, well, posted on October 25, 2010 at 22:44:53
Ted Smith
Manufacturer

Posts: 10297
Location: Seattle
Joined: December 29, 2000
Howdy

Unfortunately tonight at a friend's house I could hear a difference when plugging my DAC into a magic outlet on an Equi=Tech trunk vs. a generic outlet :( Using the Equi=Tech outlet revealed a tiny bit of haze in the high frequencies. Since the board is already floating and the balanced power shouldn't matter it must be some grunge on the power line that's leaking thru my supplies. On the other hand he can hear a difference with every piece of gear he has and his gear isn't cheap :)

I should have posted a more thoughtful response to your ALW suggestion: I agree with essentially everything you say about them but
1) I was doing my own board for my own learning experience
2) these are my 2nd attempts at power supplies, on the last board I still used 723 based supplies but they were all over the map on accuracy, let alone that they have a low bandwidth (which can be good for this purpose) and I had to backstop them with bulk, local and bypass caps.

The ALW's didn't seem like a good match for me on a few fronts:
1) not surface mount
2) no good spec on the current output (I need approx 500mA for each analog supply and about 800mA for the ECL (tho it could be split...) and 300mA for the FPGA/CMOS.)
3) they specifically warn against having the amount of capacitance that I consider necessary after their regulator. In my quick and dirty simulations modeling ideal power supplies as a dirty voltage source thru an inductor and a resistor I found that even with very low impedance in the lower freqs I needed serious bypassing/local bulk at 22MHz to keep my THD down. Getting supplies/bypassing that could get the resultant THD down far enough took a lot of work.
4) NIH :)

That isn't to say that I don't use similar quality components with some bootstrapping, etc. but I'm sure that AW or WJ could easily do better than me at power supplies.

-Ted

 

RE: My new DAC (long, but with pictures), posted on October 26, 2010 at 01:17:10
quirck
Audiophile

Posts: 213
Joined: December 23, 2006
Hi Ted,
Forgive my ignorance but which DAC chip is used?

 

RE: Oh, well-everything counts, posted on October 26, 2010 at 02:27:37
fmak
Audiophile

Posts: 13158
Location: Kent
Joined: June 1, 2002
The mains PS is very important. I separate digital and analog supplies with isolation transformer and a regenerator. They make a substantial difference as well as the regenerator frequency!

All this stuff about ALW is way over cautious. There are NO stability issues and nothing I'd thrown at it has created a problem. The ALW comfortably supplise 5V 500 mA (should do more) and is cool at that rating, and I have used many for all kinds of duty. The pregulator makes a difference in terms of ultimate noise which is about 5-7 uV 1MHz only when connected to a digital circuit. There is a SMT version as well. The lowest noise LT regulators are way noisier, no matter how they are bypassed.e




 

RE: My new DAC (long, but with pictures), posted on October 26, 2010 at 04:30:02
rsub8a
Manufacturer

Posts: 38
Location: Middle Delaware River Valley
Joined: July 29, 2006
Wow... that is impressive. That must have been one happy day for you!

 

RE: Oh, well, posted on October 26, 2010 at 06:10:20
rick_m
Audiophile

Posts: 6230
Location: Oregon
Joined: August 11, 2005
Hi Ted,

What, designing this was more interesting than chatting with us? Your layout and approaches look great, and this from a HW guy.

What's an 'ALW'?

Regards, Rick

 

RE: Oh, well-everything counts, posted on October 26, 2010 at 07:24:09
Ted Smith
Manufacturer

Posts: 10297
Location: Seattle
Joined: December 29, 2000
Howdy

Thanks. Some of your statements are at odds with his documentation, tho I can understand why he would be conservative.

I wouldn't have bothered if I wasn't going to beat the low noise LT regulators by a bunch :)

-Ted

 

No DAC chips, it's just a filter of the DSD stream, posted on October 26, 2010 at 07:43:02
Ted Smith
Manufacturer

Posts: 10297
Location: Seattle
Joined: December 29, 2000
Howdy

Thanks for asking: I was afraid I didn't make that clear :)

Like most highly integrated chips DAC chips have to make some compromises, e.g.:

1) Built to a price
2) Caps are extremely expensive on a chip
3) Digital filters are usually very "optimized" and compromises are taken
4) Current capacity and/or voltage limits force you to have either low output levels or a active amplifier
5) There may be features or bugs that may get in the way achieving the full promise of a given design.

DSD is designed so that a DAC is just a low pass filter so that's what I did: lowpass filter an amplified DSD stream. That way I can have the benefits of no active parts in the output stage (quiet, low distortion, etc.) I'm still using the same passive output as my initial prototype pictured in the original post.

I amplify the DSD stream so that I don't suffer from the worst problems of most passive output stages: low levels and a lack of punch or dynamics.

By designing both the digital path and the output to have a factor of 4 in headroom I don't get some of the compression or glassiness that I hear in many players playing high volume level dynamic music like full orchestras or full voiced women.

-Ted

 

RE: Oh, well, posted on October 26, 2010 at 07:57:49
Ted Smith
Manufacturer

Posts: 10297
Location: Seattle
Joined: December 29, 2000
Howdy

Thanks. The company that did the physical board assembly seemed surprised that I was one guy in a basement and I was a little surprised that they didn't have many other "hobbyist" customers: they mostly support Boeing, Microsoft, various local medical companies and obviously a lot of small and medium sized companies.

An ALW Super Regulator supplier:
http://www.at-view.co.uk/alwsr.htm

The super regulator has a long history and rather than confusing the issue or taking forever I'll just give you a link to the beginning :)

http://waltjung.org/Regs.html

-Ted

 

RE: Oh, well-everything counts, posted on October 26, 2010 at 08:09:13
fmak
Audiophile

Posts: 13158
Location: Kent
Joined: June 1, 2002
I think they might have arisen from the development stage and from the Jung articles.

Certainly I have made and measured quite a few (>10), added decoupling and never had a problem.

 

RE: My new DAC (long, but with pictures), posted on October 26, 2010 at 16:05:10
Rod M
Web Geek

Posts: 16200
Location: So. California
Joined: March 1, 1999
Contributor
  Since:
March 1, 1999
Long time, no see.

What are all those little cans on the board?

-Rod

 

Just say "I built my own discrete DAC goshdarnit!" :-), posted on October 26, 2010 at 16:12:47
Christine Tham
Reviewer

Posts: 4839
Location: Sydney
Joined: December 29, 2001
Much better than "it's just a filter off the DSD stream" :-)

 

They're full of electrons :), posted on October 26, 2010 at 16:20:12
Ted Smith
Manufacturer

Posts: 10297
Location: Seattle
Joined: December 29, 2000
Howdy Rod

Actually they are electrolytic caps (mostly Panasonic FK high reliability and high temp)

I use them mostly for front end filtering on the power supplies and also for bulk storage near where the current is used.

-Ted

 

That's why you write English and I write code :) [nt], posted on October 26, 2010 at 16:21:48
Ted Smith
Manufacturer

Posts: 10297
Location: Seattle
Joined: December 29, 2000

 

If you are thinking of offering your DAC for sale ... I'll help you write the marketing blurb, posted on October 26, 2010 at 17:09:18
Christine Tham
Reviewer

Posts: 4839
Location: Sydney
Joined: December 29, 2001
I think you should consider gauging interest from inmates and then doing a limited manufacturing run ...

I'm sure you are already thinking along similar lines - I'm just doing an extra bit of encouragement ...

 

Well, I knew that I just knew enough to be dangerous...., posted on October 26, 2010 at 17:12:39
Rod M
Web Geek

Posts: 16200
Location: So. California
Joined: March 1, 1999
Contributor
  Since:
March 1, 1999
I was thinking that they looked like caps. Wow, talk about cost no object. Any guess on the parts cost in audiophile volumes?

-Rod

 

RE: If you are thinking of offering your DAC for sale ... I'll help you write the marketing blurb, posted on October 26, 2010 at 17:22:04
ted_b
Audiophile

Posts: 803
Joined: January 14, 2001
Ted,
I would be very open to understanding what the costs would be of making a small batch for us asylumers. I have had close to a dozen DACs in-house over the past year, and although not in the market for a Meitner DSD transport, would love to explore what the options are for capturing DSD and hirez PCM in a less-than-$5k dac. There are some nice musical yet detailed 24/ 192 DACs out there but doing hdmi de-embedding to grab 24/88 pcm'd sacd is not the cleanest answer for DSD of course.

 

RE: Well, I knew that I just knew enough to be dangerous...., posted on October 26, 2010 at 17:26:23
Ted Smith
Manufacturer

Posts: 10297
Location: Seattle
Joined: December 29, 2000
Howdy

I wasn't sure if you were pulling my chain or not :)

I have enough SACDs for now so I can afford to make them sound better :)

I hope things are going well for you and yours.

-Ted

 

RE: If you are thinking of offering your DAC for sale ... I'll help you write the marketing blurb, posted on October 26, 2010 at 18:11:50
Ted Smith
Manufacturer

Posts: 10297
Location: Seattle
Joined: December 29, 2000
Howdy

I've done the typical engineer thing: doing the fun part without knowing where they'll go after that...

I wasn't trying to drum up business :) In fact I sort of despise some people on a few other fora that shill their own projects to drum up demand for a "group buy" or then start offering kits.

In truth I've been down in my basement all by myself so long that I sort of miss the Asylum and other human interaction. (Well I don't want to discount my wonderful wife, not everyone is fortunate enough to be able to pursue a project like this.)

I guess I was looking for a little validation from my online friends :)

Also, now that this thing works reasonably well it's time to change gears: I'm serious about either using it for a resume or somehow finding some funding. I know that I'm an engineer not a president/marketing guy/manufacturing guy or whatever. Learning new technical things is what I enjoy and am good at.

To get the costs down to something reasonable I'd have to do at least one more turn and I'd need input on what people really want. If I make a deal with a company or whatever I'd be looking for their input: USB? Dual AES cables? CD Text, Track and time decoding and display? A volume control? Multichannel? Vertical packaging into a complete system or just a box that works with x, y and z standard inputs? Field upgrade of the algos? DXD support? The list is endless and I know from experience that the features I value aren't necessarily those that most other people value.

If I were to just concentrate on, say, a low cost kit for friends (and I have gained new friends recently :) I'd be quite concerned that I couldn't make many of them mutually happy and the whole thing would turn into a drag. Also I'd either have to have a complete turnkey product or give out enough schematics, code, etc. to allow people to work on their own devices. This would clearly screw my chances of selling the tech to a company...

-Ted

P.S. Just in case I didn't use enough :)'s above:
:) :) :) :) :) :) :) :) :) :) :) :) :) :) :) :) :)

 

RE: If you are thinking of offering your DAC for sale ... I'll help you write the marketing blurb, posted on October 26, 2010 at 19:09:11
Christine Tham
Reviewer

Posts: 4839
Location: Sydney
Joined: December 29, 2001
I know you have started companies before and have been very successful at it, so this advice is going to sound like carrying coals to Newcastle at best, and downright patronising at worst.

It's tempting to polish up the product and add extra features to make it marketable, but I would suggest the product is pretty marketable as is. The extra features can come as an enhanced version later.

And if you feel guilty, you can always offer the enhanced version at discount to people who bought the first version.

Just acting as a crass commercial Steve Jobs (the evil version) to your Steve Wozniak.

 

RE: Following on from Tony's suggestion ..., posted on October 27, 2010 at 06:52:29
fmak
Audiophile

Posts: 13158
Location: Kent
Joined: June 1, 2002
That's right. dCS implments all functions thru banks of FPGAs - no commercial chips and their units sound good and measure well.

The integrity of signals thru the digital pathways is also important and their pro units come with graphs which I verified to be correct. In contrast, quite a few other makes have poor signal symmetry or integrity. Basically, the tolerance of many of these flip flops is poor.

 

RE: Thanks, posted on October 28, 2010 at 17:36:20
John Swenson
Audiophile

Posts: 2422
Location: No. California
Joined: October 13, 2002
I'm doing something very similar to Ted, I'm using the smallest FPGA that Altera makes and can easily do a 1K FIR with 58 bits internal precision.

I think the issue was using FPGAs with builtin DSP "cores", you had to live with their bit limitations. But for a simple thing like an FIR you can just use the normal gates and use whatever bit depth you want.

Ted brings up an interesting point about coefficient optimization, thats something that rarely gets discussed and can be very important. Building the whole thing out of just the random gates lets you do strange things like use 28 bit coefficients.

John S.

 

RE: Thanks, posted on February 21, 2013 at 18:25:23
PET-240
Audiophile

Posts: 5
Location: Brisbane
Joined: August 9, 2012
Not sure if Im a member here

 

RE: My new DAC (long, but with pictures), posted on February 21, 2013 at 18:28:06
PET-240
Audiophile

Posts: 5
Location: Brisbane
Joined: August 9, 2012
Hey Ted,

really amazing, old thread I know, just on a learning curve regards DSD, may I ask the config of your filter for the output stage please?

Many Thanks and I hope all is well.

Cheers,

Drew.

 

RE: My new DAC (long, but with pictures), posted on March 28, 2014 at 09:35:18
John925
Audiophile

Posts: 1
Location: Taiwan
Joined: March 26, 2007
Ted,

Could you please shed some light on how to make Meitner SACD transport work on your prototype DAC board? It is believed that ST Optical transmitting DSD is EMM's proprietary format.

 

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