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In Reply to: RE: EMI/RFI, eye patterns, and buffering posted by Tony Lauck on September 08, 2011 at 13:05:34
"...something that could be tested by running the computer entirely off of batteries if that wasn't already done"Gordon used a Macbook running off it's internal battery for the test he described.
"...since the buffers are supposedly dealing with bits whereas in reality they are dealing with analog signals"
Tony,
Does it seem possible (to you) that poor quality of the analog signal being interpreted/analysed by the USB receiver chip could stress (or otherwise impact) the chip's performance in such a way that other aspects of the DAC's performance (such as it's clocking function) could be impacted?
clay
Edits: 09/09/11Follow Ups:
"Does it seem possible (to you) that poor quality of the analog signal being interpreted/analysed by the USB receiver chip could stress (or otherwise impact) the chip's performance in such a way that other aspects of the DAC's performance (such as it's clocking function) could be impacted?"
It's certainly plausible. One would have to know more about the innards of the USB receiver circuitry. At least one can be quite certain that the timing of operations done by the receiver chip will be affected by the waveform that arrives. As a result, the pattern of electrical activity inside the walls of the DAC box will vary as a function of the signal quality entering the box. Whether or how much this affects the analog output depends on factors that only Gordon is privy to.
For another example of how this happens, one can look at the ESS SABRE chip which includes an SPDIF receiver. The timing of the SPDIF receiver circuit operation can definitely affect the analog output of the chip and this issue was specifically discussed by the chip designers in their technical white paper. As I recall, they put the high power circuitry off chip as a result of this issue.
In addition the data must be buffered and reclocked somewhere inside the DAC. Even if there is no coupled noise on the clock circuitry the timing of the data arriving at the buffer register will vary with the operation of the USB receiver circuit. It is possible that this will modulate the output of the buffer, depending on the circuit design, layout, power and ground associated with the buffer circuit. Digital buffer circuits are generally designed to reduce input variations in their output signal to a certain amount but what is needed for correct operation of downstream digital logic is far less critical than what is needed when the output signal is turned into an analog signal. (So, for example, if there is a 10% variation in clock timing or a 10% variation in signal levels or a 10% variation in rise time this will have no effect on downstream logic, but if this variation appears at the actual switching circuitry it will utterly destroy the performance of a DAC.)
In principle one could run circuit simulations of the buffer and clock circuitry and see how well they filter out these variations, assuming the circuit design details were somehow available. (These will be available to designers of mixed signal components such as DAC chips, but I don't know about DAC designers who buy their logic components off the shelf.) In addition, simulations are only useful if they can be validated by real-world data otherwise one is dealing with an unproven model. (That's the problem with the "scientific" predictions of global warming based on computer models.)
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
"It's certainly plausible."
Thanks Tony, I've wondered about this for a long time, but assumed that since no one else seemed to be suggesting this as a possible explanation - for say, why usb cables or software can make a difference - that it must not be possible for reasons I didn't understand.
thanks, as always, for your cogent explanations.
clay
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