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'near' zero volt bias for low level stages
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Posted on September 11, 2013 at 01:53:40 | ||
Posts: 394
Location: S.A. Joined: March 27, 2004 |
Hi, I'm experimenting with an idea that I read about. It uses the output current of a D/A chip across an I/V resistor to bias the tube analog stage. Its a combination biased stage, with -66mV provided by the -2mA current output across the 33R I/V resistor, supplemented by the plate current through the 12R current sense resistor in the cathode circuit. Maximum signal voltage across the input of the tube is ~132mvAC p-p. Using 6922 @ 12mA effective bias is -66mV - 144mV = -210mV no measurable grid current, every thing is fine. Using 6072A at 3mA effective bias is -66mV - 36mV = -102mV, and all is ok, all though the 12AY7 curves suggest this one is ok even biased +ve at the grid to 1V ? (wheres the current go?) What I'm wanting to use is a single dual triode with higher gain but I'm unsure as to what makes a candidate suitable for this type of stage. I am considering 6SL7. Output impedance is not a concern as it would be loaded with a CCS and the output taken from the 'mu' node, perhaps a couple hundred ohms. What I am concerned about is whether there are particular types of tubes that are more prone to grid current issues and also non-linearities when biased so low. In this example, the 6SL7 would be operating at a constant 2mA plate current, biased at (-66mV grid - 24mV cathode = -90mV). Maximum signal half cycle would peak at (-90mV + 66mV) -24mVDC grid and should set up at between 100 and 120V plate to cathode. Any hints, suggestions or comments are appreciated. Thanks, Shane |
thanks (nt), posted on September 14, 2013 at 00:59:28 | |
Posts: 394
Location: S.A. Joined: March 27, 2004 |
Thanks Mr T. |
Thanks, Lew. (nt), posted on September 13, 2013 at 23:34:12 | |
Posts: 394
Location: S.A. Joined: March 27, 2004 |
Thanks, Lew. |