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Two stage PLL

I don't know for sure what they use, but sounds like a fairly typical 2-stage phase lock loop design, whereby the first stage is in the input receiver (note that the commonly used input receivers such as the CS8412/14 I mentioned above don't really have any jitter rejection in the audio band, and create quite a bit of their own), and then the clock is filtered by another PLL with a much lower cutoff frequency. This is usually the first step that is taken by most manufacturers to lower clock jitter, and is fairly effective, but never as much as the advertisements claim. Only so much you can do with a filter, and they are almost always implemented in the same clock domain, meaning that some of the input jitter gets to the new clock directly, without being filtered. And if using a narrow band VCXO, you need a separate one for each clock rate, usually 11.2896M and 24.576M to cover the multiples of 44.1K and 48K.

Much more effective are those rare few that isolate the secondary PLL from the input stage, and run it at a very low frequency as a VCXO driven multiplier to reconstruct the clocks in a "clean" domain, thus not syncing to each clock cycle. The "new" master clock can be nearly free running in this configuration, maybe only adjusted with an integrated current charge every few seconds to maintain sync, and if the system is designed with care, can lead to very low jitter. I've built systems like this and measured data correlated clock jitter reduction of over 1000x when comparing the input receiver master clcok to that at the D/A convertor.

Some of the original Mark Levinson DACs in the mid 90s used a somewhat similar approach, though I believe they relied on a microprocessor and programmable DAC to adjust the control voltage on the VCXO about once every second.



Edits: 01/29/09 01/29/09

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