In Reply to: RE: Approaches to reducing jitter in Audio Note Dacs posted by Dynaudio_Rules on January 28, 2009 at 16:39:01:
But they don't use any jitter reduction, and unfortunately the Crystal CS8412/14 type input receivers used produce a lot of data correlated jitter on the clocks.
Goes to show that low jitter isn't necessarily required for satisfying digital music reproduction, though a DAC like this does mean you have to be more careful with the transport and interface to minimize source jitter and achieve a good match.
To answer the original question, the PLL feedback components can sometimes be optimized to help improve the jitter rejection of the input receiver with your setup since you probably aren't as concerned as the manufacturer is with fast clock acquisition and maintaining lock over a wide frequency range. Try a larger capacitor for starters. Beyond that, you would need to make circuit changes.
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Follow Ups
- diminishing returns? - Slider 20:23:59 01/28/09 (5)
- Related Question on "dual clocking" and buffering... - AbeCollins 08:38:28 01/29/09 (3)
- Two stage PLL - Slider 09:02:52 01/29/09 (2)
- RE: Two stage PLL - AbeCollins 09:10:18 01/29/09 (1)
- You need to buffer a few bits to avoid dropouts - Slider 09:21:05 01/29/09 (0)
- Thanks... - Frihed89 04:05:44 01/29/09 (0)