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In Reply to: RE: question is: posted by John Swenson on June 16, 2011 at 13:06:15:
It may not be covered by the SPDIF specification, but I'll bet most SPDIF transmitters when synced to an incoming clock have a constant output frequency and phase (plus the usual jitter due to cables and electronic devices). This means that one can use synchronous detection if one can arrange the phase (strobe time). For short cables it is probably not even necessary to provide the necessary adjustment. In other words, there would be no need for an SPDIF decoder, not even one that didn't use a phase lock loop. Of course the data rate with this encoding is twice as high as would be needed with a simple NRZ code, such as can easily be used with the separate clock line. That would be even better as it would simplify the synchronization at the decoder. If I were going about to isolate a DAC from a computer, I would be inclined to a two box solution, the first box comprising the computer interface (e.g. Async USB) and connected to the second box with an IIS interface with clock coming from the DAC and data going to it. If variable phase delays were needed at this point they could be achieved by tuning the length of the cable between the two boxes or by building a variable delay into the converter box, again keeping the maximum amount of logic aware from the box that contains the clock, converter and analog circuitry. (This style I/O interface is hardly original and was developed by Seymour Cray in the 1960's for the I/O channels used in the CDC 6000 series computers.)
I am inclined to take this even a step further and remove all the DSP processing from the DAC box. This is certainly possible if one uses a 1 bit output at which point any required PCM conversion to bit stream could even be done in the computer system. With such a system there would be no digital logic in the DAC box with the exception of data buffers and clock buffers and the analog switches and the box would contain only a single clock domain. The metric for "good design" in such a system would be to minimize the number of gates. Unfortunately, I've not yet convinced myself that a one bit design is going to work well to my standard as I don't like high frequency noise. If you go to multibit you are talking FPGAs or custom chips to do the necessary dynamic element balancing (e.g. DCS ring DACs and ESS Sabre chips) and one has complex digital logic in the box, i.e. problem not solved.
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
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Follow Ups
- Some random thoughts... - Tony Lauck 14:55:35 06/16/11 (0)
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