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RE: And I would like to see Justice For All, while we're at it.

"How do you know this? There is no point in speculations that you cannot substain in reality. DAC design is constrained by physics and perhaps not as much as the politics in computer design and marketing."

This is what DAC designers report. It is also something that is obvious if one looks at some of the circuits involved (e.g. the circuitry associated with logic gates and flip flops considered as mix-signal devices). It is also consistent with the work you've been doing to clean up power wiring inside your PC based transport. More to the point, if several stages of logic buffering are used each stage will provide a certain amount of attenuation of the noise, which attenuation will be cumulative except for coupling means other than the intended signal path down the pipeline.

Note: I am considering only proper clock architectures, those in which the transport is slaved to the DAC clock and not the other way. These can be realized with separate clock wires going in the reverse direction using AES/EBU or SPDIF, with block mode USB, Firewire or Ethernet, or asynchronous USB. There is no need for variable frequency oscillators or any kind of phase locked loops in a proper clock architecture. (Even without this it is possible to build working systems that will run for a limited period of time without losing sync with a large enough buffer and sufficiently accurate clocks, but this is a separate subject.)

Tony Lauck

"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar

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