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In Reply to: RE: 1) without a doubt, #1 is digital source jitter posted by Wesley Miaw on April 7, 2012 at 12:59:01:
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buffer and reclock the incoming S/PDIF stream so that the outgoing signal jitter is entirely dependent on the chip's driving clock.
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I do not think that is what the paper describes. It shows an improved version of PLL with less jitter than older "conventional" methods. But the output clock is still a (less) jittery PLLed clock to keep the elastic buffer as they call their reference buffer all the time partially filled. And that is always the case if two independent clock domains are to be aligned (input SPDIF, precise clock for the receiver). IMO the only way to go is to use some form of feedback, somehow controlling the pace of the incoming data. Be it PCI via IRQs, or USB/firewire async via feedback control messages.
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Follow Ups
- RE: 1) without a doubt, #1 is digital source jitter - phofman 13:32:30 04/07/12 (4)
- RE: 1) without a doubt, #1 is digital source jitter - Wesley Miaw 14:07:14 04/07/12 (3)
- RE: 1) without a doubt, #1 is digital source jitter - phofman 00:03:41 04/08/12 (2)
- RE: 1) without a doubt, #1 is digital source jitter - rick_m 16:51:41 04/08/12 (0)
- RE: 1) without a doubt, #1 is digital source jitter - Wesley Miaw 05:23:48 04/08/12 (0)
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