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Critic's Corner Discuss a review. Provide constructive feedback. Talk to the industry. |
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Critic's Corner Discuss a review. Provide constructive feedback. Talk to the industry. |
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In Reply to: Now you've got me curious posted by Charles Hansen on April 10, 2007 at 20:06:11:
The capacitance still varies, but there is less R-C time delay associated with the variation.I spoke with the designer about it at a CES/THE show. It is a way of increasing the carrier concentration without high electrical bias.
The package is there to keep the outside world away from the silicon die. For example, EPROM memory chip packages have expensive little windows in them to allow the UV light, but nothing else, to penetrate. Dust, dirt, polluted air, and humidity will combine to contaminate the exposed surfaces of the silicon die, create leakage paths, and encourage corrosion of the metal leads and bonds. Cutting open a transistor package is not something I would do.
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Follow Ups
- No, it doesn't reduce capacitance, just the parasitic resistance. - Al Sekela 09:51:18 04/11/07 (0)
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