Home Tweakers' Asylum

Tweaks for systems, rooms and Do It Yourself (DIY) help. FAQ.

The ol' workhorse 8412

24.4.254.56

Hmm, I couldn't quite fully translate the data sheets and tech support either; it appears the word select [l/r] output is derived from the preamble so supposedly has less correlated jitter; however, as we have found it is generally better to reclock the with the 256 fs externally.

I have extracted a 2 fs signal from the SPDIF/AES preamble with couple of politically incorrect monostables. This might be useful for reclocking/registering a DAC that updates with a latch enable transition such as the AD 1865, 1862, or BB 63; but is mostly useless
with the type of DAC that updates on a clock cycle after a latch enable transition like the BB 1700, 1702, 1704. The 1541 can be either depending on the input mode selected, but at 1x fed by the 8412 in 1^2s mode, it is in the latter category.

After mulling a bit [pun], maybe the "old" 8412 is not ready for pasture, or the glue factory just yet. Especially with TSE so rampant. The "newer" ones that are 96 kHz ready have the laws of physics working against them: a higher frequency range vco has a higher K sub o which means the vco control pin, like the loop filt pin, is _more_ sensitive, not just to intended signal, but also noise. Generally, the narrower the band of a vco, the lower the phase noise and jitter. Granted, there are heoric engineering feats to make up for handicaps, but the laws of physics do in a Zen like way point towards lower bandwidth vcos as the way to go.

Hey, the trick of 75 ohm terminating/matching the cable and using it as a DC path is a totally kewl one that does not strictly follow standards, but is fair game in DIY land. A tradeoff is you give up ground isolation that transmormer coupling provides, but quite likely you more than make up for that with less interface high pass [ low freq rolloff ] issues.

One of these days when in the mood for a flame war we should start a string along the theme of perceptual significance.

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