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In Reply to:
I think the concern expressed by the original poster... posted by **Charles Hansen**
on June 21, 2017 at 14:09:10:

Charles, as you correctly surmised, I was addressing synchronous interpolation digital filtering in my upthread comments. I don't disagree with your pointed criticism of ASRC. As I understand it, the main problem with ASRC solutions is the operation of the 'ratio estimator' block. This block is tasked with determining the ratio of the input to output sample rate. The resulting ratio estimation is computed by taking a running average of the two rates, which can vary or drift slightly in value over time and thus provoke artifacts. In addition, very small rate differences, where the input and output rates are nearly, but not quite, the same can also provoke ratio estimator artifacts.Artifacts appear because the programmable filter coefficients (which are derived from the ratio estimator's computations) utilized in the rate conversion/interpolation polyphase FIR filter block are themselves interpolated values. This is done in order to compute coefficients which support arbitrary input/output ratios. One of the problem aspects of ASRC design seems to be insufficient polyphase filter coefficient precision, which is magnified in hardware based IC converters due to limited hardware resources.

Just my very much non-authoritative understanding of the underlying problems. Perhaps, someone with ASRC design expertise will add to, or correct my above basic assessment.

_

Ken Newton

Edits: 06/22/17 06/22/17

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Follow Ups

RE: I think the concern expressed by the original poster...-knewton07:24:41 06/22/17(0)