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Upsamplers, DACs, jitter, shakes and analogue withdrawals, this is it.

I think the concern expressed by the original poster...

When performing synchronous interpolation ("upsampling" or "oversampling"), generally the original data points are still present (although often scaled in value), and additional interpolated points are calculated between the already-existing data points.

In contrast when performing asynchronous interpolation, virtually *all* of the original data points are discarded and replaced with calculated values. In the very best case of a common asynchronous rate of 44,100 to 48,000 samples per second, there would only be one original data point every 147 or 160 samples (depending on the direction one is converting), as those are the least common multiples of the two rates. (In practice this has never been achieved as doing so would require interpolating by either 147 or 160 and subsequently dividing by 160 or 147. The resultant intermediate frequency of 7.056MHz is too great and capable chips priced too high to be available in any known equipment. It is past double-DSD rates but would require 64-bit accumulators rather than the single bit used in DSD.)

Instead what is used is an ASRC (often also used as a "jitter eliminator") wherein the incoming and outgoing rates have no correlation whatsoever. In that case, every single output sample is an *interpolated* value. While each output sample is *related* to the input samples, the relationship is known only to the designer of the particular algorithm used by the ASRC chip.

My personal experience, and what appears to be a broad general consensus, is that synchronous interpolation (wherein the original sample points are retained or scaled) is sonically preferable to asynchronous interpolation (wherein the original sample points are completely replaced by interpolated values).

As always, solely my personal opinions, prone to error, and not necessarily those of my employer or pool-boy.

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