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Upsamplers, DACs, jitter, shakes and analogue withdrawals, this is it.

Those points seem arguable to me

To begin, I think you would agree that you're generating the same amount of jitter when recovering the clock as other DACs that use the CS8414, although you or any of the other DAC designers could argue that their own circuit layout, power and/or other elements of the design lead to slightly less jitter on the recovered clock in their DAC. But most of those items are, from my own experience, completely swamped out by the huge amounts of jitter on the recovered clock from the CS8414 due mainly to bandwidth restrictions in the interface and improper termination causing irregular but often data correlated rise and fall times on the incoming data from which the clock is recovered. I've no idea where your 240ps susceptibility figure comes from since even the 256 fs master clock on the CS8414 running at approx. 11.2896MHz (and which I assume you don't use for anything in your DAC) has a period of 88000ps, doesn't it? A non oversampling design would have a bit clock period 8 times as big! You can definitely hear the levels of jitter you're speaking of, but not because they are causing bit errors.

I would agree that digital filters do potentially introduce a lot of extra jitter into a system, but it wouldn't be transport dependant, although it still may be data correlated as much of the worst interface jitter is.

I just don't see how one can claim that a non-oversampling design will have less transport dependant jitter on the bit clock at the D/A convertor. But I guess from your post you aren't claiming that, instead you're saying that because the clock rate is lower that the effect will be less and I'm not sure I buy that since either clock would have the same jitter spectrum from the transport.

Interesting discussion though.


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