But the whole problem is **how** this jitter is "eliminated"....... What happens is the time shifted data is re-sampled by the precise output clock, but because the data being sampled was time-shifted (due to the input jitter), the sampled data isn't at the correct amplitude. (The time shift means the output grabs the amplitude from the signal, interpolated at an extremely high rate, slightly before or after where it should have taken place.) This is where the whole problem is.
"2. In a proper implementation of ASRC it may be necessary to interpolate the output signal,"
It is not only necessary, but it wouldn't otherwise function in this particular implementation...... (I think you meant to say "input signal.")
"since the input signal may appear between two output samples. If one does not do this, then there will be, as you suggest, jitter introduced."
That's not where jitter is introduced, at face value. What happens is if the input signal is time-shifted from jitter, which the intermediate interpolated signal is correlated to, what's sent to the output will not be of correct amplitude, and these amplitude errors, which is a function of the input jitter, introduce noise.
"However, on can interpolate the output sample if one knows the time factor involved (see next paragraph)."
I'm not sure what you mean by "time factor"...........
"Jitter in the input timing is eliminated in a proper ASRC by using a digital phase lock loop."
The PLL supposedly reduces jitter, whether it's ASRC or not. The PLL is not unique to ASRC playback. Many older synchronous conversion DACs use PLL for jitter reduction.
"This can be designed to have an extremely narrow lock bandwidth, a minute fraction of one second if desired. The limit is given solely by the long term stability (drift) of the oscillators and the acquisition delay (e.g. when the input source goes from one nominal sampling rate to a new one). There is nothing to preclude (in a sophisticated design) a wider initial bandwidth for rapid lock coupled with an increasingly narrow bandwidth once the input oscillator has been observed to be stable in frequency. A very small FIFO is used (perhaps only a latch) to accommodate the input jitter, and the output comes out at known points. (The ideal jitter free sample times computed by the digital PLL are referenced as fractional values measured according to the output clock which is the stable oscillator.) The resolution of these virtual times can be made arbitrarily large by representing them as binary fractions. The net result is that the uncertainty in timing can be reduced to a tiny fraction of an output clock sample. The known timing between samples is then input to the interpolation algorithm (next step)."
Useful for those who want an idea how a PLL works.............
"3. The final stage of the process is to calculate an output sample. This occurs at integer clock ticks according to the output sampling rate. The input samples appear at constant periods not necessarily related to the output sample times. If one uses a zero order hold for the interpolation, one will get your jitter. But one can use as good interpolation as one wishes. For example the ASRC in the 24 bit SABRE chip uses 1st order interpolation at an output sample rate around 40 MHz. If this isn't good enough, one could use even higher order interpolation."
What gets lost here is the intermediate interpolated signal is still correlated to the *input*....... (The PLL might reduce it, but it's still there.) Once again, if there is a shift from jitter, what's actually sampled to the output, which is from that interpolated signal, will contain an amplitude error, due to the sample being grabbed slightly before or after it should have been.
