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In Reply to: RE: So... any idea why both of Wavelength and Ayre sound better,... posted by Todd Krieger on November 02, 2009 at 00:15:11
"That IMO would likely be the main "technical" reason why the Ayre and Wavelength would sound better."Sorry Todd. While your old post may be applicable to some implementations of ASRC, it is not necessarily applicable to all implementations. Perhaps the ASRC in the Benchmark isn't good enough. I don't know, as I haven't heard the product or seen the necessary technical details (except that the output sample rate of 110 kHz seems inadequate on the face). IMO it is inappropriate to reject a design approach qualitatively, if there is a possible good implementation of that approach. However, one needs to carefully select any listening tests and/or measurements based on the technical approach in a product, if one wants to do a good job of evaluation.
I will now address each of your three points in your original post.
1. In particular, the whole point of using ASRC is to allow the use of a fixed output clock, something which can be built at much lower intrinsic jitter than a variable clock as needed for an analog PLL. It would be stupid to use this mechanism and not use a high quality oscillator, except for a cheap implementation where ASRC is used to eliminate the need for separate clocks for the 44.1 x n kHz and 48 x n kHz families of sampling rates.
2. In a proper implementation of ASRC it may be necessary to interpolate the output signal, since the input signal may appear between two output samples. If one does not do this, then there will be, as you suggest, jitter introduced. However, on can interpolate the output sample if one knows the time factor involved (see next paragraph).
Jitter in the input timing is eliminated in a proper ASRC by using a digital phase lock loop. This can be designed to have an extremely narrow lock bandwidth, a minute fraction of one second if desired. The limit is given solely by the long term stability (drift) of the oscillators and the acquisition delay (e.g. when the input source goes from one nominal sampling rate to a new one). There is nothing to preclude (in a sophisticated design) a wider initial bandwidth for rapid lock coupled with an increasingly narrow bandwidth once the input oscillator has been observed to be stable in frequency. A very small FIFO is used (perhaps only a latch) to accommodate the input jitter, and the output comes out at known points. (The ideal jitter free sample times computed by the digital PLL are referenced as fractional values measured according to the output clock which is the stable oscillator.) The resolution of these virtual times can be made arbitrarily large by representing them as binary fractions. The net result is that the uncertainty in timing can be reduced to a tiny fraction of an output clock sample. The known timing between samples is then input to the interpolation algorithm (next step).
3. The final stage of the process is to calculate an output sample. This occurs at integer clock ticks according to the output sampling rate. The input samples appear at constant periods not necessarily related to the output sample times. If one uses a zero order hold for the interpolation, one will get your jitter. But one can use as good interpolation as one wishes. For example the ASRC in the 24 bit SABRE chip uses 1st order interpolation at an output sample rate around 40 MHz. If this isn't good enough, one could use even higher order interpolation.
If one wants, one can built a system where input jitter has no effect on output jitter, measured down to the least significant bit (or even lower if desired) of the output samples. In other words, there would be no discernible jitter on the output of the sample rate conversion, as could be determined by looking at the digital samples. (There would still be jitter on the output analog signal due to the jitter of the output master clock, and if this weren't completely isolated electrically from the processing done by the ASRC function then there could still be coupling introduced this way, but this would be a criticism of the implementation of the ASRC, not its architecture.)
In short, there is no theoretical reason why an ASRC need corrupt the signal in any way shape or form. In practice, of course, that's another matter. Many ASRCs are used primarily as a cheap digital way of eliminating a more expensive crystal oscillator. The new Wavelength option is going to use the 32 bit SABRE chip, which has an ASRC as an (optional) feature. Gordon will have to comment on whether he will be using this feature or not. Presumably he will make this determination based on sound quality, as the cost of an extra oscillator isn't likely to be terribly important at his price point.
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
Edits: 11/02/09Follow Ups:
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