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I think I may have a partial explanation of the well reported lock-on issue of the AES16 interfacing with an external clock.One of the clocks is 49.152 MHz, which is an exact division by 256 to 192k.
However, the other is 45.168 MHz which when divided by 256 gives 176.4375 kHz. On my system the clock rate for 176.4 k is reported by the card to be 176.4391MHz. Both are more than 200ppm greater than the nominal frequency. This may account for the drop in drop out behaviour and the incomatibilty with the clocking from dCS clcok outputs. In reality, the AES 16 has difficulty both with Big Ben and with clock out on a UA2192 as well.
If true, this is bad design. In the manual, Lynx stresses the importance of narrow plls to kill jitter. If the pll lock-on centre frequency does not correspond accurately to the incoming stream's frequency, then one would expect problems!
On the Lynx forum, there is no acknowledgement of this issue up to a year ago when I gave up looking 'cause I was getting silly answers. Lynx appears to blame this on dCS until then.
Note: I also had a card with aes plugs that won't fit into a standard socket; too big!
Edits: 11/03/09 11/03/09Follow Ups:
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