Computer Audio Asylum

RE: Update v0.3: The Art of building Computer Transports

24.195.131.234

In Reply to: RE: Update v0.3: The Art of building Computer Transports posted by cics on September 14, 2007 at 15:07:18

I appreciate the effort you have documented here on PCs, as it has a lot of information I've never seen before. It may also be useful to people who are using PCs to do testing and measurement with PCI cards (audio frequencies and higher), you may want distribute the link people on those groups as well.

One thing I do want to bring up - you are making great efforts in the PC, only to then send out the digital data via SPDIF / toslink optical cable to a DAC.
It would seem to me that the efforts should be made in the DAC, where the data is converted to audio. If the DAC has a REALLY effective VCXO based 2 stage PLL, (with local crystal oscillator and reclocking at DAC), then the efforts on the transport side from the PC, especially with optical isolation *should* have little effect. If the DAC does not employ the above technique, (or a local master clock sent back to the soundcard), you are not close to optimizing what you can get in terms of low jitter at the DAC chip, especially using toslink. The process of converting electrical to optical and back again using the toslink connectors creates a lot of jitter, which can be easily measured. Because the SPDIF receiver needs to lock to many different frequency standards, it has a wide bandwidth PLL based on a VCO, that creates a lot of jitter in the process. In many popular receiver designs (CS8412 for instance) there is essentially no jitter reduction below 20kHz!

So efforts upstream may be audible, but the SPDIF receiver is still the weak link in the chain unless there are heroic efforts downstream that involve a local crystal and reclocking. In theory, at least, which in audio may not go too far sometimes :-)
Bob

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RE: Update v0.3: The Art of building Computer Transports - cics 14:24:52 10/04/07 (0)

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