In Reply to: Single Clock Domain. Otherwise madness! posted by Tony Lauck on March 26, 2012 at 10:37:50:
"SPDIF is a bad system design"
Yes, it is indeed. I'm not sure what the SOTA currently is in reclockers but that functionality really belongs inside the DAC housing so it can use the D/A clock.
But since you are "assuming that the input has already been synchronized into a single local DAC clock domain", the SPDIF issues are mute.
"The data signal will have noise, in the form of timing variations and amplitude variations, to be dealt with as below."
Here is where I get boggled, you can run it through all the inverters and shift registers in the world at this point but you won't improve the S/N. Once you've got a steady local clock that occurs well out from the settling time of the signal transitions, your done. You just dump it into your D/A converter chunk.
The reason that additional stages don't provide further isolation is because every gate decodes every bit and regenerates it using the rails as the ideal. The main source for amplitude variations in the signal at the clock point of the next device is noise on the power and ground and that's largely constant for all gates powered by the same planes.
I suppose the current issue is why Async DACs aren't immune to cable variations. Well, I bet they are more immune than the average bear because they eliminate the need for a variable clock in the DAC which can be a problem, especially if implemented with a VCO. Depends on the implementation of course but "fixed" is the limit of "variable" so they are hard to beat, all else being equal. But outside of improving the local clock issues all the other sneaky paths and problems remain and without delving into specific implementations further speculation seems futile.
Please don't think I am trivializing these issues but we are discussing stuff at the level where implementation is inseparable from performance. Without simplifying assumptions life as we know it would grind to a standstill so they are crucial, but we dare never regard them as givens. You are assuming the 'source contamination' is somehow propagated by the signal and probably some of it is, but I assume more of it is via the power planes and probably some of it is. Some of it is bound to come from EM coupling and that has many paths. Ground loops between gear are really likely to be a term on paths without galvanic isolation. It never ends, all we can ever do is try to have sufficient specifications so that implementations that meet them will have inaudible levels of artifacts. Well, that's the engineering take, marketing knows it ends when the CTM is low enough for good margins and the performance adequate to keep most of the rubes from returning it after they have been spurred into buying by advertising.
Regards, Rick
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Follow Ups
- RE: Single Clock Domain. Otherwise madness! - rick_m 08:36:48 03/28/12 (3)
- RE: Single Clock Domain. Otherwise madness! - Tony Lauck 09:40:45 03/28/12 (2)
- RE: Single Clock Domain. Otherwise madness! - rick_m 07:48:38 03/29/12 (1)
- RE: Single Clock Domain. Otherwise madness! - Tony Lauck 08:14:15 03/29/12 (0)