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In Reply to: RE: Reminder... posted by fmak on March 25, 2012 at 11:05:51:
Any timing variations that don't move the data through the 0.5 level around the time the data is buffered into a flip-flop won't affect the results further down stream. There may be issues with amplitude variations, i.e. a 0 isn't a fully black zero and a 1 isn't a fully white one. However, logic gates and flip flops include level restoration circuits which have the effect of severely attenuating variations in signal provided it is relatively close to a 0 or a 1. This will definitely be the case after the received signal has been buffered once by a local clock. Each stage of digital restoration will necessarily attenuate any remaining amplitude variations. This is the basic reason why digital computers work. (See figure 5 of the linked page which includes a reversed "S" curve showing how degraded digital signals are improved by a stage of digital restoration as included, say, in a gate.)
Given that each stage necessarily attenuates these variations the questions that remains are: How many stages are necessary? Is there some way that an unwanted signal can bypass these stages and escape some of the attenuation? To answer the first question one must decide how much attenuation of unwanted signals is required (e.g. 20 dB more than the signal to noise ratio available in the analog circuitry) and how much attenuation each stage can provide. (This will require detailed characterization or accurate simulation of actual circuits used.) To answer the second question one will need to look carefully into the complete layout and circuitry of the product. For example, any power supply wiring and power supply circuitry provide a coupling path for unwanted signals, even those from devices that aren't having anything to do with the actual audio processing. If unwanted signals are leaking around through power wiring and power supplies this is not really a matter of the signal path and similar things can happen with circuits that aren't even carrying audio related signals. Saving money by putting most of the digital logic into a FPGA is probably not going to hack it if one is trying to get truly excellent results. In the very good ESS white paper on the SABRE chip the authors describe how on-chip ground bounce related to the timing of incoming SPDIF signals managed to pollute the output analog waveform of the chip and what they had to do to minimize these effects.
As expensive and difficult as this may be, there is some hope of success if a DAC designer sets out to do this. A software hacker trying to achieve similar effects by tweaking a general purpose computer system to minimize noise at its source has zero chance of success and will be on a constant upgrade path to nowhere.
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
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Follow Ups
- RE: Reminder... - Tony Lauck 12:36:25 03/25/12 (7)
- RE: Reminder... - rick_m 09:07:24 03/26/12 (6)
- Single Clock Domain. Otherwise madness! - Tony Lauck 10:37:50 03/26/12 (5)
- RE: Single Clock Domain. Otherwise madness! - rick_m 08:36:48 03/28/12 (3)
- RE: Single Clock Domain. Otherwise madness! - Tony Lauck 09:40:45 03/28/12 (2)
- RE: Single Clock Domain. Otherwise madness! - rick_m 07:48:38 03/29/12 (1)
- RE: Single Clock Domain. Otherwise madness! - Tony Lauck 08:14:15 03/29/12 (0)
- RE: Single Clock Domain. Otherwise madness! - rick_m 17:52:12 03/26/12 (0)
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