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RE: Jitter reduction mods

65.19.43.59


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You can eliminate data correlated jitter by replacing the CS8412/14 with a CS8415A. The CS4812/14 PLL recovers the clock from the data transitions; the CS8415A uses the preamble transitions. After that, random clock jitter is insignificant compared to data correlated settling time and the 11us interchannel time delay in all AN DACs. The former can be reduced and the latter eliminated with the addition of a few shift registers.




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