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In Reply to: RE: PLLXO question related to LDRse posted by JBen on February 26, 2012 at 12:56:15:
You have to consider/include 'everything' when designing PLL's. :) Even interconnect capacitance might be an issue.
You can measure output resistance of a source fairly easily. Take a voltage measure unloaded and also with a 1k resistor attached.
Rout = 1000 times (Ropen-Rload)/Rload
You'd be surprised how high the source resistance is on many components.
Cheers,
Dave.
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Follow Ups
- RE: PLLXO question related to LDRse - Davey 13:03:15 02/26/12 (3)
- RE: PLLXO question related to LDRse - neolith 14:01:37 02/26/12 (0)
- RE: PLLXO question related to LDRse - johnvb 13:12:44 02/26/12 (0)
- RE: PLLXO question related to LDRse - JBen 13:11:31 02/26/12 (0)
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