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In Reply to: Jitter-practical case for 2nd PLL posted by Pooge on June 23, 2004 at 10:31:21:
The real problem to solve is to provide a jitter-free clock to time the digital to analog conversion. This is the only thing that you hear. Jitter at previous points doesn't matter if you can eliminate it at the DAC.Also, a separate clock versus a derived clock is not an issue. Separate crystal oscillators have jitter. Even with an I2S interface with its own crystal oscillator there would be some jitter. The CS8416 does a very good job (not perfect) of providing a low-jitter clock. I suspect that it is on the order of a good (not perfect) crystal oscillator.
So you take the output from either a crystal oscillator or derived clock and send it through a second PLL like the Tent clock to clean it up and you end up with the same thing. This may be the reason why some DACs sound the same with either the I2S or S/PDIF interfaces.
Dave
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- More jittery thoughts - Dave Davenport 13:02:05 06/23/04 (1)
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