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Asynchronous USB vs Asynchronous DAC

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Posted on August 27, 2009 at 13:59:18
Sordidman
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 or, are we talking about the same thing?

I apologize in advance if this subject has been previously covered: but I'd like to ask please; what and why is Asynchronous different than Synchronous DAC design? And how does that relate to clocking, and the PLL?

It is my understanding that my stacked AKM DAC boards in my APL have clocks built into the DAC boards so that eliminates the master clock. Is that what defines asynchronous?

Again, - after a cursory search, - I didn't see much talk of this.

Thanks in advance for any thoughts.

Surrendered to self preservation,
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But hurts just like anything else.
Please refrain from polluting this forum with, posted on August 29, 2009 at 09:44:41
bjh
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 technical/scientific discussions!

;)
Everything matters, don't forget to tweak your placebos!
RE: Asynchronous USB vs Asynchronous DAC, posted on August 27, 2009 at 17:37:43
Tony Lauck
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 Completely different architectures:

1. transport has clock. DAC slaves to the transport using a PLL

2. transport has clock. DAC has clock. DAC uses asynchronous sample rate conversion to adapt the two clocks to each other.

3a. DAC has clock. DAC sends clock back to transport, causing transport to send data back at the rate determined by DAC clock. Separate clock line goes from DAC back to transport as in AES connections or some I2S setups.

3b. DAC has clock. Transport has clock, which runs at approximately correct rate. DAC has a buffer to accommodate differences for short perioeds. DAC sends signals back to transport telling it to speed up or slow down as needed, which prevents the buffer from overflowing or emptying out.

Note that I have grouped 3a and 3b, because these are equivalent. Both of them allow the DAC to control the speed at which the transport sends.

Any of these approaches may work well or poorly, depending on implementation. Unfortunately a good implementation of the first approach requires a low jitter PLL. This requires a stable variable frequency oscillator as part of the PLL. Something that is at once stable and also variable is a rare animal. Hence the first approach, while it seems OK in theory, fails in practice. The other approaches can all work well. However, the logic to implement asrc properly is complex and most implementations have been poor quality, so asrc has gotten a bad name in some circles.


Tony Lauck

"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar

Thank you Tony! Really appreciate that great explanation, posted on August 28, 2009 at 08:51:44
Sordidman
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 Also,

I forgot about the relationship between the transport and DAC stage; each does "clocking:" (except in the case of number 1).

And, - not all DACs have PLLs; right?


Thanks again Tony, appreciate it.


Surrendered to self preservation,
From others who care for themselves.
A blindness that touches perfection,
But hurts just like anything else.
RE: Thank you Tony! Really appreciate that great explanation, posted on August 28, 2009 at 09:32:20
Tony Lauck
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 "And, - not all DACs have PLLs; right?"

Yes. But most do, at least hidden inside the chips. Even if the audio clock that controls the D/A conversion isn't transmitted across the link from transport to DAC the data is transmitted sequentially, and there has to be some kind of a data transmission clock. At the end of the cable a clock is needed to separate out the received pulses and look at the waveforms at approximately correct times, hopefully when they are stable and not while they are in the process of changing. Even in the case where the original clock was in the DAC and was sent to the transport and back to the DAC, it will be necessary to time the exact instant the bits are available, and while this will be at the frequency of the local clock in the DAC the delay will depend on the length of the cable, etc., so some mechanism will still be needed to find the center of each bit.

If the data and clock are multiplexed over the same wire (as with SPDIF and USB) there will be timing variations due to the signal and often a PLL is used to generate the data clock used by the receiver circuitry. But in the good clock architectures, this clock is just used to store bits into a buffer memory and not to actually time the audio samples. It needs to be good enough to decode the bits properly but this is 100 times less critical than what is needed to convert the digital samples to analog, so there shouldn't be a direct concern here. Unfortunately, some PLL circuits use a lot of current in their operation and this current can introduce undesired electrical interference that can pollute the analog components, affect the critical master clock that controls the A/D converters, etc. so there can still be ways that jitter in the interconnect can end up altering the sound in practice, even if it shouldn't happen according to theory.

There are still several more layers of the onion that can be peeled back, but I may have already gone into more detail than may be useful to you.

Tony Lauck

"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar

RE: Thank you Tony! Really appreciate that great explanation, posted on August 29, 2009 at 17:11:57
Sordidman
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 ""There are still several more layers of the onion that can be peeled back, but I may have already gone into more detail than may be useful to you.""

Not at all, - but is it sinking in? That could be another story. :-)

I appreciate you taking the time, = I want to get a better understanding of clocking and bits through time.

I am particularly interested in AKMs implementation, and APL's. As I understand it, I have 8 DACs per channel, (2 DAC boards per channel with 4 DAC chips on each), and was curious if there is a clock on each DAC board, or built into each DAC, as also, - there is no master clock. And, it's Asynch; so I was curious how this all fits with Asynchronous conversion.



Surrendered to self preservation,
From others who care for themselves.
A blindness that touches perfection,
But hurts just like anything else.
RE: Thank you Tony! Really appreciate that great explanation, posted on August 29, 2009 at 17:55:34
Tony Lauck
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 I can't tell you how your DAC works, unfortunately. With good documentation your questions may be answerable, or possibly with reverse engineering, but that can be a huge amount of work. (I've done some reverse engineering of computer networking products in several patent lawsuits, but I had the benefit of Discovery and was ultimately able to gain access to the source code in the chips. Not something I would or could do on a hobby basis.)

There are various reasons for using multiple DAC chips and various techniques for doing so. Some chips, such as the ESS SABRE chip, include this ability internally (8 channels separately or 2 stereo channels). Of course the trick is keeping them all synchronized.

Tony Lauck

"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar

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