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In Reply to: RE: ASRC not necessarily bad. posted by Tony Lauck on November 02, 2009 at 19:49:14
"1. Error in estimating the time at which the input signal should have arrived if it were jitter free."
Since PLLs have been common prior to ASRC (my Prism DA-2 DAC uses it), if it completely eliminated jitter (it doesn't in the real world), then using ASRC to eliminate something that was *already* eliminated would be pointless. (Unless variable input or output rates were to be utilized, which is the one thing ASRC has over synchronous conversion. A true jitter-free input signal would eliminate the noise issue. But no ideal exists in the real world. And still, the ASRC isn't what would even be actually eliminating the jitter. It would only benefit from the PLL doing so.)
"2. Error in performing the interpolation between output clock points due to inaccurate algorithm. (Reduce this error by using a higher order interpolator or a higher output sample rate or a combination of the two.)"
I'm not sure what you mean by "between output clock points"...... The interpolation is actually performed *prior* to the output clock sending samples to the output. The samples sent to the output are *already* interpolated. (This is why if there's jitter on that interpolated signal, which is correlated to the input signal/PLL, the errors at the output would be that of amplitude/noise.)
"3. Error in calculating the interpolated values. (Use a longer word length in the interpolation calculations.)"
With the sheer speed of the calculations in such high oversample rates utilized in ASRC, this *might* be an issue. But to be honest, I think the jitter in the signal would likely result in larger errors, unless some calculations were corrupted outright. (Such errors would render a DAC unusable.) The output is good enough (in this context) to quench such doubt.
I think the ultra-high oversample rate performed in ASRC in itself is a technological achievement. (The processing power has got to be downright immense.) But since there is no readily explicit information on how these values are actually generated, I'd raise the question in regard to short-cuts possibly being done in order to achieve such high oversample rates.
At the end of the day, I think asynchronous conversion should have never seen the light of day in consumer CD playback. And also consumer CD recordings. I think CDs cut from a high-rez 24/192 master is a similar compromise.
I'm sorry that my explanation was difficult to understand. It's a difficult subject, and no doubt the inherent difficulty has resulted in many designs that don't quite work correctly. For a description of some of the compromises applied in practical designs (which have been reported by audiophiles to be good sounding) look at the white paper for the ESS SABRE chip and the patent filing on ASRC technology by the authors of the paper.
There is no point in arguing the case against using analog PLLs to derive sample clocks. This has been discussed numerous times in numerous threads. If you have one that has low enough jitter that it doesn't bother you, then I'd just enjoy it.
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
I listened to the SABRE chip at the L.A. Can Jam several months ago. It was actually one of the better performers there. Although it was with music that I was unfamiliar with, so I couldn't really compare it to anything.
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As I understand it, it is possible to bypass the ASRC on the SABRE chip if one runs the chip with a master clock that is an appropriate multiple of the sample rate. That would be up to the DAC, i.e. if it didn't use the built-in ASRC it would probably need to have two different master clocks to accommodate the 44.1 and 48 kHz families of sampling rates.
Do you recall the DAC that was running at the demo?
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
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