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In Reply to: RE: Thanks for the good wishes. posted by Ted Smith on January 09, 2011 at 12:46:12
It's your project and it's for you to say what it's goals are and whether or not they have been (adequately) met. All and all, I think you've done a great job and provided an inspiration to many as to what can be done in a DIY project. Thanks for taking the time and effort to post about your project and putting up with the various flac that has been returned. :-)
There is one point where I personally would have slightly different goals had it been my project, so if you don't mind I'd like to clarify one point.
".) Some said (and still say) that a proper FIFO is sufficient to get rid of jitter. Once again that's obviously false to me but obviously true to the bits-is-bits people. I defy anyone to find a fault in my FIFO implementations or to build a FIFO that works gets rid of all audible effects of jitter."
A proper FIFO is necessary to get rid of jitter. It won't be sufficient, as there can be other jitter coupling modes, e.g. power used by input decoding stages can couple through power and ground into output clock circuitry. In addition, a FIFO may work perfectly at moving bits, but fail to achieve jitter isolation. Such a FIFO will be suitable for some applications, e.g. a buffer in computer interface, but not suitable to achieve jitter isolation in a DAC. Each component in the DAC FIFO needs to be modeled in the analog domain and the jitter attenuation of the FIFO as a whole needs to be modeled and verified empirically. Until this has been done it's not possible to conclude that a given FIFO is "proper" for the DAC application. I suspect there are many FIFO architectures that work satisfactorily for pumping bits that fail to achieve additional jitter attenuation when cascaded. This will depend on the circuit design, layout and, especially, the clock architecture. There aren't a lot of components (e.g. transistors) in some FIFO designs, so it would seem possible to design in such a way that each stage of the FIFO provides a constant (dB) attenuation of jitter. It looks to me like you've got most of the tools at hand to investigate this aspect of the design, should you decide to do so at some point in the future. However, if your FIFO is in the FPGA there may be no way to achieve sufficient isolation, due to the design of the cells and/or the available wiring.
It won't be possible to get perfect isolation, nor is it necessary. The effect of jitter is to introduce noise modulation onto the output analog signal, and if you can get this noise modulation well below the output noise of the DAC itself that will be sufficient. Modeling and measuring the jitter related output noise caused by the available degree of isolation won't be easy, but it can be done and must be done if one wants to solve this problem.
It is also possible that the audible effects of changing the transport have nothing to do with jitter, or even to do with the DAC. There could be other modes of coupling (e.g. RFI/EMI) to the downstream analog components. There are probably experiments that can be devised to evaluate these coupling modes.
The only other part of your discussion that I could possibly disagree with concerns power cords. But I'm not really interested in power cords, since all the evidence seems to indicate that the effect of power cords depends on all the components in the system and the general electrical environment. If I were a fanatic about power cords, I would just get rid of them completely e.g. run my components on internal batteries. :-)
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
Follow Ups:
Howdy
A few minor points: a FIFO can't provide "constant jitter attenuation". It is at best a low pass jitter filter: you can talk about the slope of the attenuation and it's corner freq, etc. In my experience as the corner frequency of the jitter filter goes down the bass gets firmer (in addition to other effects.)
I've also wanted to try the opposite experiment: instead of trying to get rid of all jitter (which paradoxically can cause it's spectrum to become more colored) perhaps whitening the jitter spectrum might provide a more practical way of achieving a cleaner sound. (Obviously I don't believe it will given the direction I've taken, but still it's a different possible approach.)
As I've mentioned in other posts I assume that jitter is sometimes the only reasonable explanation for the effects of changing, say, a power cord. In the specific case I've talked about before the transport and the DAC were connected by glass fiber so along that path the only possible effect is jitter (or bit errors). The transport was 10' away from the DAC and the rest of the system so I don't expect that RFI was significant. The DAC, the transport and the other system components were on separate dedicated circuits so the AC coupling was fairly minimal, tho possibly audible. But now with further experience with jitter's audible effects I recognize that the firming of the bass when the transport had a more substantive power cord is one common effect of lower jitter. I don't claim this would convince someone else, but it's personal experiences like this that help to clarify one's journey in understanding (or at least rationalizing) "audiophile tweaks", in this case power cord effects and jitter effects.
It's a little off topic, but I often wish I could have more "bits-is-bits" (or objectivist) people over so they could hear for themselves the effects of some simple experiments: we could then do other experiments to help them clarify possible mechanisms in their own minds. I've found over and over that when even some of the die hard double blind proponents hear a significant difference sighted often it opens their eyes to possible explanations for the effects they hear in ways that no amount of discussions will.
-Ted
I'm not sure we are communicating regarding what a FIFO can and can't do as regards removing "bits ain't bits". Or perhaps I'm off base and have been consistently missing something.
I'm not really concerned about the rate adaptation function of a DAC FIFO, as this can be dealt with by the clock architecture (e.g. slaving the transport to the DAC master clock). It looks like you've solved the problem for most interesting cases, as you can make the corner bandwith of your digital phase lock filter effectively zero once you've found a frequency setting that drains the buffer sufficiently slowly that no changes in rate are needed through the course of an entire track. The key to this, as it was obtaining stable jitter with the FDDI reclocking system, is to use buffer load state as well as rate differences as input to the feedback loop. My understanding is that you are doing this.
The other problem arises if you just take a jittery signal and reclock it with a clocked flip flop.(Here I'm talking about what is going on within a single clock domain.) The output transitions are supposed to follow the local clock, not the transition times of the input signal so long as the setup and hold times have been met. Of course they do not do so exactly, but the question is whether the net effect of the flip flop is to attenuate the variations. If so, then it should be possible to string a bunch of flip flops in series with appropriate clock scheme and achieve any desired degree of attenuation. I suspect the problem is that the output level of a gate depends slightly on all the input signals (e.g. the output of a NOR gate will be at a slightly lower level if all the input signals are true compared to just one) and the propagation delay through a gate depends on the level of the input signals. Perhaps your SPICE simulations are such as to demonstrate this phenomenon (or lack thereof).
Tony Lauck
"Diversity is the law of nature; no two entities in this universe are uniform." - P.R. Sarkar
Howdy
The issue is how do you clock those flip flops without having the signals going into the first flip flop affecting it's clock or power supply ... and hence the clock or power supply of the final flip flop... If you get into it further it's the same problem as using a PLL to attenuate jitter: you are at best are filtering the jitter and that filter isn't as simple as uniform attenuation. TANSTAAFL. Tho I don't have the proof at hand I believe that once again the best you can do is some form of low pass filtering of the jitter. In the limit tho low passed jitter becomes wander and wander slow enough to not affect the bass firmness isn't a problem.
I'm sure that I've posted my implementation of the idea you are talking about elsewhere but here's a synopsis:
I use a FPGA to do the bulk FIFO storage. The FPGA outputs a clock and the data associated with it and these signals go into a high quality flip flop to align the signals with a separate clean power supply. Then the signals go from that flip flop to another with it's own PS which is clocked directly by the master clock (with it's own PS and thru only a few mm of traces.) And when I say "own PS" I'm not just talking about a local ferrite bead and some caps.
The initial mistake I made was to clock the two external flip flops exactly out of phase with each other which is almost the worst timing possible: the only worse timing would be to clock them in phase. The beauty of FPGAs is that I only had to change one parameter to advance the FPGA and it's flip flop 90 degrees and make a significant difference in the audible jitter. Taking this lesson to the limit you can see how there isn't room for an arbitrary number of flip flop stages: you eventually are switching some of the flip flops too close to the switching of other flip flops and increasing the possibility of jitter leakage thru the power supplies or clocks.
I'm not claiming that this proves my case, but just like other "jitter solutions" things aren't as simple as a first level analysis might lead one to believe.
-Ted
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