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The data does cause clock jitter

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In Reply to: RE: Contamination as in Electircal Noise posted by cics on March 26, 2008 at 23:51:16

Any time data is moved from one point to another in an audio digital component, that data can modulate the clock because of real impedances in the circuit traces, and in the D/A convertor chip itself. This is especially problematic at very low audio signal levels in a PCM-based system because the two's complement data words go from all zeros to all ones at or near the zero crossing point, and so the music signal, which is repetitive by nature, can easily couple to the clock as data correlated jitter.

As an example, consider a digital filter outputting a 1Khz low level sine wave encoded data signal, along with the bit clock and word clock to the D/A convertor IC. Each of these signals must 'travel' from the digital filter IC to the DAC IC and back. All share the same reference at the DAC IC, but the average level of the data line will alternate between a high and low state, causing the power and the ground to change during the time as well because of the impedance of the power and return paths. This changes the clock threshold level in the DAC IC (as well as modulating the clock amplitude at that same 1KHz rate) resulting in data correlated jitter. Even if the jitter was zero at the output of the digital filter, it is present at the DAC (and easily measurable I might add).

This is the same type of situation you have with asynchronous clocks running a FIFO or any other buffer device. The input clock modulates the time and frequency parameters of the output clock (and vice versa) because they are connected to the same device and hence share the same power and ground system. In addition, the data will modulate the clocks as previously detailed. Every edge transition or level change in the system creates a background of noise on the power and ground lines that will ultimately modulate the clock at the DAC IC. In order to effectively remove the jitter and not reintroduce it requires isolation techniques that are not commonly used and are somewhat expensive to implement.

Follow Ups:

RE: The data does cause clock jitter - cics 11:13:30 03/31/08 (0)
Very interesting and makes a lot of sense.

With lower levels we get no information in the higher order bits thus alternating signs cause signal changes from largely all 0's to 1's as you mention. This data related noise probably gets worse with increasing frequency as there's more frequent swings between signs (with same amount of unused higher order 0's and 1's).
RE: The data does cause clock jitter - audioengr 16:30:06 03/29/08 (1)
Many implementations do suffer from ground-bounce and crosstalk, so I agree this can be a problem. I have found that designs in the field of consumer electronics are frought with these problems, even from large multinational companies. Many of the mods that I have done in the past repair these types of problems.

I implement many of the isolation techniques you mention in my own products, so I dont have this problem. My circuits behave closer to the ideal. Separate power feeds, isolated return traces, effective decoupling and termination/impedance matching etc..

This is simply ground-bounce and crosstalk between traces and with power supply. With proper circuit design and board layout, these can effectively be minimized so that they are inaudible.
- Inaudible to you ... may not be inaudible to others - Slider 18:33:46 03/29/08 (0)
  But I haven't heard your stuff so can't comment on that.
  
  I think we've talked about this before, but separate return paths don't really effectively address the problem since the signals generally all share the same source and return pins. Better to have a close layout with an extremely low impedance return path (typically an uninterrupted ground plane directly above the signal traces) except this isn't always possible if you want the digital filter and all of the other high jitter signals isolated from your clean clock and D/A convertor.
  
  One method that works pretty well for me is generating the clocks in an isolated section (using BB ISO 150 device) along with the D/A convertor and analog stage, and then clocking the data across the barrier. Not perfect, and everybody has their own way, but you have to break the jitter path at some point.

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