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In Reply to: RE: Do you mean ASRC's? posted by Scrith on March 27, 2008 at 02:15:49
This concept is similar to DAC as clock master architectures. These approaches still have unwanted jitter distortion.
DAC's local clock will have timing errors that displaces samples in time. Such large buffers will add to DAC's complexity and has the potential to make it worse.
(sorry for the delay in replying...I never bothered to follow-up on this analysis because it would soon be irrelevant)Yes, there will always be jitter somewhere deep inside the DAC (hence the opportunity for academics here...a neverending source for analysis!).
But, if the jitter is taking place entirely within the DAC itself, with no external factors influencing it, there is no need for a study of jitter from software, drivers, cables, source components, interfaces, power supplies or quality in equipment other than the DAC, RFI/EMI, etc. In other words...the post is moot if one simply uses a DAC that does not rely on the timing of incoming data (and I don't mean by merely using a buffer to reduce the effect of incoming jitter...I mean dictating the flow of data asynchronously).
By the way, DACs that support asynchronous input are now available (from Ayre, Wavelength, and others in the near future).
Edits: 04/08/09