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In Reply to: RE: Contamination as in Electircal Noise posted by cics on March 26, 2008 at 23:51:16
"If there's ripple voltage riding on the data input single (for example), are you saying this will NOT impact jitter? If so, how?"
If the setup and hold times are not violated, then the data will be clocked into the first flip-flop inside the D/A chips without error. If it meets these criteria, then only the clock that clocks the data has any effect on the timing. This is fundamental synchronous logic 101.
"Data sent to chip is at bit level where the bit clock matters. How else would the chip determine actual signal amplitudes (16 or 24bit)?"
Data sent to the chip is either ones or zeroes. It is the output of the D/A where the voltage varies. The contents of each data frame on the input determines the word size. The frequency of the input stream to the D/A chip determines the sample-rate.
There is a lot of misinformation and misunderstanding of these processes. Listen to the engineers that have the education in these areas.
Steve N.
What you explaining is how the chip accurately decodes binary signals, so setup and hold times are important in this regard.
On data input, looking at the AKM DAC example, the following is explained in its operation:
In all modes the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK.
It goes on to explain that BICK must present and so on...
What you avoiding is the lack of noise immunity thats riding these signals. A Flip Flop is a switching circuit that still maintains current flow. Noise coupling remains a factor.
cics and all of his groupies should read:
http://boards.psaudio.com/showthread.php?t=3412
http://www.psaudio.com/newsletters/3-08.asp
Bottom line, a Toslink digital output from a stock soundcard isn't going to produce SOA results no matter how much plug and play PC tweaking cics does.
PS- cics have you ever built or modifed/upgraded any DAC?
Noise coupling is not a factor. The data has almost a full half cycle of setup and hold time with respect to the clock rising edge. There are no violations, therefore noise on the data signal is not a factor. Only the noise on the bitclock (SCLK) is a factor.
The kind of noise you are talking about is well below the switching threshold in 99% of designs. If this is not the case, then the design is severely broken and should be redesigned anyway.
Steve N.
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