Computer Audio Asylum

Posted by cics (A) on March 25, 2008 at 06:59:46

In Reply to: RE: Jitter Research, Analysis & Measurement posted by audioengr on March 24, 2008 at 22:53:51

I have not found this to be true at all, in fact most D/A converter chip datasheets actually say that the conversion occurs on either the SCLK (bit clock) or the MCLK (master clock), not the word-clock. This is a common misconception.

This may be chip dependent. Point is a clock is marshaling when samples are dispatched be it LRCK, MCLK or other. Whichever one used would trigger the jitter distortion.

Reducing jitter in all of the I2S clocks will achieve low jitter in the resultant conversion. I'm not sure I understand what you are saying in your conclusion. There are certainly a lot of sources of jitter in the typical digital streaming logic chain. In your case, you evidently had a mixture of ground-loop noise and jitter, and a miriad of different devices, probably all with non-ideal S/PDIF and clock interfaces. Do you know if the clock cables were impedance matched and properly terminated?

No myriads of devices in play - just Transport and DAC (and AMPs - no preamp). Component not in use (Scarlatti or AA) is physically disconnected. For soundcard, the one not in use is disabled. Therefore only ONE SPDIF input is connected. No ground loop problems like humm etc..

Clock cables from Crystal as well as dCS stock version.

What I'm saying is: yes a clean clock signal is important and will give sonic benefits as you mention (through reducing jitter). But its not the only factor. My experience suggests care must be taken across all clock inputs as well as data inputs. This is more challenging.

It reads that you are comparing a Transport DAC combination to RME and Juli@t PCI boards, and the RME board was slaved to the external Scarlatti Clock? Is this correct?

Its the total combination (transport, soundcard, DAC) that I'm looking at. Juli@ also performed better when compared to both RME & Scarlatti DAC clock slaved. Currently, RME provides master clock (Juli@ is disconnected - used for recording). For slave configuration, when using AA DAC (which does not allow for clock slaving), only RME can be slaved.

So-called "noise-pollution" and "RFI" etc. are all words that describe phenomenon that are widely misunderstood. These are usually ground-loops causing "ground-bounce" or they are simply crosstalk or power supply noise.

Ever wonder why using a superclock with measured jitter performance below a ps results with DAC jitter thats much higher? This after great care is taken in its implementation (including excellent grounding and power supply). The noise pollution includes EMI (as in induced currents), RF pickup (into GHz), IMD, signal reflections and thermal noise.