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196.11.134.77
In Reply to: RE: Jitter Research, Analysis & Measurement posted by Sunya on March 24, 2008 at 14:23:41
Did you try to slave the cMP directly to the Scarlatti DAC since the Scarlatti DAC also has an word clock output?
There is a thread on the Slim Devices forum about slaving the Transporter to an external DAC and from the discussion it seems it's better to use the DAC as Master, thus running from its internal clock and send that clock to the slaved source, than to slave both the source and the DAC to an external master clock like the Scarlatti unit.
The RME jitter specification is quoted to be <1ns; I can't imagine it providing a better clock and sounding better in master mode than slaved to the Scarlatti DAC. Why not slave it at 44.1k, disable the SRC and let the DAC make any upsampling?Here are a few quotes form the founder of SD from the thread I gave the link in case you didn't had time to read it:
Quote:
Yes it is a manual setting. Please, notice that I use a DAC and en external clock, i.e. two units.?!? Why?
Such a configuration should only be used if you have some requirement to synchronize multiple _source_ components, perhaps for editing purposes.
It is the MCLK (eg 11.2896MHZ) signal that actually drives the internal operation of a modern DAC chip, and the whole point of word clocking (for the purpose of reducing jitter) is to put that clock as close as possible to the DAC chip itself.
A PLL is absolutely _terrible_ at generating a master clock from a word clock, compared to generating it directly with a crystal. But that is not even the only source of jitter - you are also accumulating it in all the connections between this equipment, and in the clock source device itself, as it has to divide a crystal-generated clock internally to produce that low word clock frequency.
I am not aware of any situation where a word clock would be advisable for driving a DAC. You will get jitter much worse than anything you'd get even from traditional s/pdif master-> slave clocking.... i.e. this is not only defeating the jitter eliminating mechanism of the word clock interface, but is actually making the jitter far worse even than plain s/pdif. You are probably running your DAC on a few hundred picoseconds of jitter, as opposed to the 30ps or less that would come from a good quality internal oscillator.
Quote:
2) Even better is to syncronize both the DAC and the Transporter to an external clock - if this clock is of higher precision than the one in the DAC.No, this is where you are very wrong. I have already explained why from a theoretical standpoint, but to put it another way, which do you expect will have more jitter:
- A crystal oscillator running at 12.2880 MH, directly driving the DAC
Or
- A crystal oscillator running at 12.2880 MHz
- driving either a synchronous counter or a series of flip-flops, to divide that signal down to 48 KHz
- then feeding this signal through some transmission circuit to a BNC connector
- coupling that signal into a cable
- feeding it down the cable
- getting it into another connector at the other end of that cable
- driving that signal into a PLL circuit which multiplies the word clock signal back up to 12.2880 Mhz
- feeding the output of that PLL into the DAC chip.
Quote:
Finally, I still can not understand your theory of internal vs external clock (high precision oscillator) for a DAC. Please, notice that both Esoteric and dCS promotes this idea - and for me it works well with the Transporter and 44.1kHz.Which part of it is unclear?
Consider an absolutely perfect clock with zero jitter. No such thing exists, but let's just suppose for the sake of argument that your external clock source is such a device.
Now, divide that clock signal down to word clock speed (/128 or /256), send it through a bunch of cables and connectors, through a PLL to multiply it back up to MCLK speed, and then across another circuit board to the DAC chip. How can that possibly still be a clean clock? How could it possibly be cleaner than if you placed the crystal oscillator right next to the DAC chip? It can not. Not by any stretch of the imagination, and not even if you consider a _perfect_ external clock source compared to the poorest imaginable local crystal clock source. It is not even close. The external clocking scheme is worse by about a factor of ten. In practice you would get about 15-50ps for the internal clock, versus 100-300ps for the external, PLL-recovered clock.
The fundamental principle of word clocking, when used for the purpose of reducing jitter, is that you are eliminating all the crap between the clock source and the DAC. This is where jitter comes from. The quality of the crystal oscillator is actually not even a major factor.
Finally ask yourself, if dCS can produce a better clock signal through such a convoluted means, why would they not then simply build this technology into their $18K(?) DAC? Maybe they just want to sell you yet another overpriced box.
Look, I am not making this up and I have nothing more to sell you. What I am telling you is all solid theory that can easily be tested with suitable equipment. Have a look at this (and also be sure to jump back to part 1 for the introduction):
http://www.tnt-audio.com/clinica/diginterf2_e.html
What you need to do is shown in the "clock backwards" configuration. This is ideal - it puts the oscillator right at the DAC so that the clock signal does not flow through PLLs, dividers, or interconnects.
If anywhere in my reasoning you have found a mistake, please point it out and we can discuss. Otherwise it's pretty silly to just not believe me because my conclusions conflict with what the high priced stereo vendors have told you. There are guys who will sell you lacquered knobs and granite isolation plates too.
Thanks for extracting the relevant bits. I'm familiar with TNT's documentation. A DAC acting as master will still have:
- Loss of galvanic isolation
- Clock circuitry from DAC's XO to deliver signal
- Interface issues (transmission circuit, cable, BNC interface, signal coupling / noise rejection,...)
My learnings suggest that even with an XO placed at the DAC chip and assuming the clock signal going into the DAC chip is clean, contamination occurs. Think about these questions:
- What's inside the DAC chip?
- Why stop just at the chip's clock input?
- What happens with all the other (untreated) signals entering the DAC?
All these additional inputs have an impact on the sample clock. There's an assumption that the sample clock remains pure within the chip. My understanding of chips suggest this assumption is incorrect. Chips internally carry tiny sample buffers, have all kinds of logic circuits to perform filtration, upsampling and so on... This complex circuit is still subject to noise entering it. That pure sample clock does not act in isolation as it is integrated and therefore susceptible to noise.
Anyway, I also plan to measure this scenario (DAC provides master clock to Transport at 88.2k). Yes clock works in multiples of master, ie. 48 will also do 96 and 192 (same applies with 44.1).
RME jitter specs of < 1ns is a guide. Its difficult for manufacturers to provide exact jitter as they have no control over PSU quality and complexity of computer environment. These factors and more destabilize the XO which by itself is actually very good (~20ps).
I cannot figure out what the heck you are talking about here.
D/A converters have four signals typically, called I2S, including:
MCLK
SCLK
SDATA
L/RCLK
Most D/A chips do the conversion on the Bit clock (SCLK) or the Master Clock (MCLK). Depends on the chip which one. The quote from the SD guy says they are all Master Clock, but this is not true. Depends on the chip.
If you lower the jitter on the SCLK, you will have succeeded in lowering the jitter in the analog output for most D/A chips.
If the Master Clock is generated inside the DAC (very rare), and then divided-down to a word-clock which is output to the source device for synchronization, this is the optimum solution. The jitter on the Word-clock to the source device does not matter, as long as its not so bad as to cause errors. This is only necessary to get clean data image into the input FIFO. Once in the FIFO, the output clock is the one with ultra-low jitter. It takes a memory-based system to do this effectively.
The same thing can be done with a memory-based reclocker that sources the master or word clock to the source device, such as the Transporter. The reclocker can then drive all four signals of I2S to an I2S input DAC. This will acheive very low system jitter. Again, the jitter in the clock that is transmitted back to the source (as slave) is a "dont-care". Such reclockers work extremely well, even though they are a "third" box in the chain.
Steve N.
If you lower the jitter on the SCLK, you will have succeeded in lowering the jitter in the analog output for most D/A chips.
I'm not disputing this. You're also correct in that the clock treatment must be on the correct clock input signal (as this varies by manufacturer). Lets call this correct clock signal the master clock.
So, what am I saying then:
- Remaining clock signals entering the chip will carry jitter which is not directly related to the master clock jitter. Of course if these are are grossly jittered other issues arise. My understanding is that for these non critical clocks, level detection is used (as opposed to phase).
- Both the clock and data inputs however carry noise. This noise infiltrates the chip. Noise as mentioned before includes EMI (as in induced currents), RF pickup (into GHz), IMD, signal reflections and thermal noise. Remaining clock signals have jitter which I see as phase noise and this adds to the overall noise contamination.
- If chips are free from such contamination entering it, then yes only the master clock signal needs treatment. This is a large assumption.
Why regard the chip as a 'perfect black box' when in fact its a (very complex) circuit? There's bound to be interference at the master clock signal which entered the chip uncontaminated. This interference manifests as jitter.
"Remaining clock signals entering the chip will carry jitter which is not directly related to the master clock jitter. Of course if these are are grossly jittered other issues arise. My understanding is that for these non critical clocks, level detection is used (as opposed to phase)."
There is only one synchronous clock used on a DAC chip. The others are not effectively clocks. Sometimes the MCLK is used to do digital filtering, but does not affect conversion, which is where the jitter becomes audible.
"Both the clock and data inputs however carry noise. This noise infiltrates the chip. Noise as mentioned before includes EMI (as in induced currents), RF pickup (into GHz), IMD, signal reflections and thermal noise. Remaining clock signals have jitter which I see as phase noise and this adds to the overall noise contamination."
No, only the single clock signal matters. Once the data is clocked into the first flip-flop in the D/A converter, only the clock matters.
"If chips are free from such contamination entering it, then yes only the master clock signal needs treatment. This is a large assumption."
The data can be jittering a lot, but it does not matter. Only the clock matters. This is fundamental synchronous logic. Contamination means nothing. There is no such electrical phenomenon as "contamination", except maybe in water sources or air etc.. It is either timing jitter, ground-bounce or crosstalk.
Steve N.
If there's ripple voltage riding on the data input single (for example), are you saying this will NOT impact jitter? If so, how?
No, only the single clock signal matters. Once the data is clocked into the first flip-flop in the D/A converter, only the clock matters.
Data sent to chip is at bit level where the bit clock matters. How else would the chip determine actual signal amplitudes (16 or 24bit)?
Any time data is moved from one point to another in an audio digital component, that data can modulate the clock because of real impedances in the circuit traces, and in the D/A convertor chip itself. This is especially problematic at very low audio signal levels in a PCM-based system because the two's complement data words go from all zeros to all ones at or near the zero crossing point, and so the music signal, which is repetitive by nature, can easily couple to the clock as data correlated jitter.
As an example, consider a digital filter outputting a 1Khz low level sine wave encoded data signal, along with the bit clock and word clock to the D/A convertor IC. Each of these signals must 'travel' from the digital filter IC to the DAC IC and back. All share the same reference at the DAC IC, but the average level of the data line will alternate between a high and low state, causing the power and the ground to change during the time as well because of the impedance of the power and return paths. This changes the clock threshold level in the DAC IC (as well as modulating the clock amplitude at that same 1KHz rate) resulting in data correlated jitter. Even if the jitter was zero at the output of the digital filter, it is present at the DAC (and easily measurable I might add).
This is the same type of situation you have with asynchronous clocks running a FIFO or any other buffer device. The input clock modulates the time and frequency parameters of the output clock (and vice versa) because they are connected to the same device and hence share the same power and ground system. In addition, the data will modulate the clocks as previously detailed. Every edge transition or level change in the system creates a background of noise on the power and ground lines that will ultimately modulate the clock at the DAC IC. In order to effectively remove the jitter and not reintroduce it requires isolation techniques that are not commonly used and are somewhat expensive to implement.
Very interesting and makes a lot of sense.
With lower levels we get no information in the higher order bits thus alternating signs cause signal changes from largely all 0's to 1's as you mention. This data related noise probably gets worse with increasing frequency as there's more frequent swings between signs (with same amount of unused higher order 0's and 1's).
Many implementations do suffer from ground-bounce and crosstalk, so I agree this can be a problem. I have found that designs in the field of consumer electronics are frought with these problems, even from large multinational companies. Many of the mods that I have done in the past repair these types of problems.
I implement many of the isolation techniques you mention in my own products, so I dont have this problem. My circuits behave closer to the ideal. Separate power feeds, isolated return traces, effective decoupling and termination/impedance matching etc..
This is simply ground-bounce and crosstalk between traces and with power supply. With proper circuit design and board layout, these can effectively be minimized so that they are inaudible.
But I haven't heard your stuff so can't comment on that.
I think we've talked about this before, but separate return paths don't really effectively address the problem since the signals generally all share the same source and return pins. Better to have a close layout with an extremely low impedance return path (typically an uninterrupted ground plane directly above the signal traces) except this isn't always possible if you want the digital filter and all of the other high jitter signals isolated from your clean clock and D/A convertor.
One method that works pretty well for me is generating the clocks in an isolated section (using BB ISO 150 device) along with the D/A convertor and analog stage, and then clocking the data across the barrier. Not perfect, and everybody has their own way, but you have to break the jitter path at some point.
"If there's ripple voltage riding on the data input single (for example), are you saying this will NOT impact jitter? If so, how?"
If the setup and hold times are not violated, then the data will be clocked into the first flip-flop inside the D/A chips without error. If it meets these criteria, then only the clock that clocks the data has any effect on the timing. This is fundamental synchronous logic 101.
"Data sent to chip is at bit level where the bit clock matters. How else would the chip determine actual signal amplitudes (16 or 24bit)?"
Data sent to the chip is either ones or zeroes. It is the output of the D/A where the voltage varies. The contents of each data frame on the input determines the word size. The frequency of the input stream to the D/A chip determines the sample-rate.
There is a lot of misinformation and misunderstanding of these processes. Listen to the engineers that have the education in these areas.
Steve N.
What you explaining is how the chip accurately decodes binary signals, so setup and hold times are important in this regard.
On data input, looking at the AKM DAC example, the following is explained in its operation:
In all modes the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK.
It goes on to explain that BICK must present and so on...
What you avoiding is the lack of noise immunity thats riding these signals. A Flip Flop is a switching circuit that still maintains current flow. Noise coupling remains a factor.
cics and all of his groupies should read:
http://boards.psaudio.com/showthread.php?t=3412
http://www.psaudio.com/newsletters/3-08.asp
Bottom line, a Toslink digital output from a stock soundcard isn't going to produce SOA results no matter how much plug and play PC tweaking cics does.
PS- cics have you ever built or modifed/upgraded any DAC?
Noise coupling is not a factor. The data has almost a full half cycle of setup and hold time with respect to the clock rising edge. There are no violations, therefore noise on the data signal is not a factor. Only the noise on the bitclock (SCLK) is a factor.
The kind of noise you are talking about is well below the switching threshold in 99% of designs. If this is not the case, then the design is severely broken and should be redesigned anyway.
Steve N.
"Both the clock and data inputs however carry noise. This noise infiltrates the chip. Noise as mentioned before includes EMI (as in induced currents), RF pickup (into GHz), IMD, signal reflections and thermal noise. Remaining clock signals have jitter which I see as phase noise and this adds to the overall noise contamination."
So isn't this a good reason to not use the clock generated by the soundcard when set to master which will then be sent to the DAC? The clock of the soundcard can't be as good as the one generated by the DAC, not to mention the PC environment isn't exactly helping.
I think this discussion shouldn't be about the shortcomings of different chips. It's all about which component should be the master for the clock generation and I hope you agree with me that the clock provided by the Scarlatti DAC should be much better then the one from the RME card.
For me the ideal setup would be:
An optical connection from the soundcard to DAC for data transmission.
The DAC set as master which will then send its generated clock to the soundcard.
What DAC do you know of that will do this?
Steve N.
Do you mean a DAC with an Optical input and an Word Clock output?
These are a few that came to mind, maybe there are more:
1. Esoteric DACs
2. dCS Scarlatti
3. EMM DACs (only ST glass)
4. Prism Sound DA-2 & Orpheus
5. Digital Audio Denmark AX24 equipped with the stereo AES-SPDIF module.
I shared your same ideal view, ie. optical input and DAC (or external clock) as master. Thats why I bought the Scarlatti Clock.
The clock of the soundcard can't be as good as the one generated by the DAC, not to mention the PC environment isn't exactly helping.
In the paper, following is mentioned:
Computers superiority in jitter performance is not well understood. Consider this: SATA specifications demand strict jitter tolerances for which standards are defined (something like not exceeding 160ps peak). Computer manufacturers utilize jitter testing equipment measuring in femto seconds (a femto is a thousand fold less than a ps)! This is all very necessary to achieve very high bandwidths and extremely low bit error ratios.
Computer manufacturers have substantially more R&D dollars to create faster, cheaper & more efficient products. Because of ever increasing performance demands (faster processors, RAM etc) manufacturers have to reduce jitter to very low levels. This is critical for achieving high bandwidths. Clever noise reduction technologies are being implemented, e.g. DDR2 that has ODT (on die termination) technology that terminates signal reflections within the memory module. Reduction in power consumption demands is also forcing the industry into creating low-power components.
Combining a soundcard (PCI, Firewire or USB based) with a computer allows one to achieve low jitter when correctly optimized. My experience suggests that soundcards have good quality XOs (a must for the recording industry where computer audio is the norm). Yes, computers are complicated animals and offers phenomenal capabilities BUT they come with configurations that suit a general PC user and NOT audio. Such configurations create lots of jitter at the soundcard. The challenge is in reconfiguring it.
Thus, a computer acting as Transport is a perfect platform for low jitter IF configured correctly. Given its processing capabilities it offers another very important benefit: high precision upsampling based on bandlimited interpolation which recreates the analogue waveform. Such reconfiguration of a computer is covered in cMP's documentation (based on Windows XP). Others provide excellent guides for Linux. When fully implemented, the results are very good indeed. So much so that it can act as clock master and question the 'DAC as master' approach! You get all this for $1500. That's how I'm experiencing it and feel compelled to share it.
Sound cards all have very jittery clocks IME. The computer has little or nothing to do with it either. I have evaluated a LOT of different clocks, and found only two that are acceptable to me. One of these is the Superclock4.
The reason that there are superior computer audio solutions to CD players is that the chips available for USB have superior digital PLL's in them. If CD players had minimal buffering and good digital PLL's they would be equally as good.
Wi-Fi has a distinct advantage because the data is networked and packetized. This allows the master clocking to occur at the destination, independent of the source.
If you are looking for really low jitter solutions, spending money on really expensive gear may not get you there. It's making the right choices.
Steve N.
Hi SteveN,
What is the other clock you found acceptable - hope it's lower cost than the Superclock4?
Do you think that 90% of the improvement in putting on a new clock is in the new cleaner/better PS that feeds the clock? If not 90% what figure would you put on it?
The other clock is a trade-secret.
Power subsystem, not just power supply makes a big impact on the superclock and other logic performance. Also the board layout and circuit board layout and design as well as transmission-line terminations and impedance matching also have a big effect. It takes all of this to achieve a really low system jitter.
Steve N.
Trade secret? Why? Is it not commercially available? Is it some new product?
Why not dispense with all this clock business nonesense & go for the ESS Sabre Multi-channel DAC which recovers the clock from the SPDIF apparently without jitter. How its' done is a trade secret but at least it is available!
Apparently? Yeah right, I've heard this before.
Why would I buy another DAC when my own design beats everything I have heard? Only Zanden 5000 comes close...
Did you had the chance to see the Stereophile measurements for the Zanden 5000? There were performed 2 measurement sessions because the manufacturer claimed the first sample was defective. Check the jitter figures on both samples, it really seems like overpriced junk in a shiny box targeted at clueless rich guys...
first sample measurements:
http://stereophile.com/cdplayers/1106zanden/index4.html
second sample measurements:
http://stereophile.com/cdplayers/1106zanden/index8.html
Just because it has high jitter does not mean that it necessarily sounds bad. The jitter spectra could be inaudible to most humans. I have customers with this DAC and they tell me is is very good. Sometimes musicality is more important than detail.
How do we measure musicality?
With our ears, in stereo.
Electronic instrumentation and classical measurement techniques are not able to do it IME. It will take a multi-dimensional measurement to do this I believe, including phase, magnitude and frequency for two channels in a two-dimensional plot. This plot will also need to be swept over gain settings so that compression due to absolute level can be observed. Nothing like this has ever been done to my knowledge.
Steve N.
Have a look over at DIYA - design engineer has been posting & sending out sample boards - so it's not marketing hype as before - it is standing up to the claims made of it!
Why the trade secret clock - you didn't answer this?
Of course I didnt answer. It's a trade secret. We manufacturers have to have some of these otherwise our competitors just steal everything and put us out of business. Patents I have lots of. They are worthless unless you are willing to spend $100K in court.
I guessed as much about your post - all smoke & mirrors ("trade secret") - just a lot of bullshit being passed off as mystique - unfortunately, a common problem in this area called HIFi!
Good to see Stereophile expose some of the pretenders, whoever they might be!
My products speak for themselves. It's all about the engineering. I'm an engineer with 30 years design experience. I dont ever lose in shootouts.
OK, I didn't realise you were a manufacturer - then it's understandable that you protect your IP, I agree.
It also explains your reaction to the ESS Sabre DAC I mentioned!
They dont allow me to identify myself on this forum. Against the rules.
If you use Superclock4 as a reference, then soundcard XOs would be poor.
Dunn suggests jitter below 20ps is inaudible. I'm using this as a reference for which professional soundcards can be compared to.
I dont give a hoot what someone suggests. In a highly-resolving, low-noise system you can easily hear the difference between the Superclock4 and a Superclock3 for instance, and they are both probably sub-100psec in jitter.
Steve N.
"I hope you agree with me that the clock provided by the Scarlatti DAC should be much better then the one from the RME card."
cics doesn't agree with this. He thinks his cMP (RME set as Master)sounds best.
I agree the clock in the Scarlatti DAC/Clock should be much better then the one from the RME card, but once you connect them to the RME card they're exposed to the noise contamination from his cMP.
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